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RTL8326
24-PORT 10/100M + 2-PORT 10/100/1000M ETHERNET SWITCH CONTROLLER WITH EMBEDDED MEMORY
DATASHEET
Rev. 2.1 27 November 2003 Track ID: JATR-1076-21
RTL8326 Datasheet
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REVISION HISTORY
Revision 1.8 1.9 2.0 2.1 Release Date 2003/05/15 2003/08/08 2003/9/17 2003/11/27 Summary First external release. Add AC/DC characteristics and mechanical information. Add thermal data Add digital timing characteristics diagram
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
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Track ID: JATR-1076-21 Rev.2.1
RTL8326 Datasheet
Table of Contents
1. 2. 3. 4. 5. GENERAL DESCRIPTION..............................................................................................................................................12 FEATURES.........................................................................................................................................................................13 BLOCK DIAGRAM...........................................................................................................................................................14 FUNCTIONAL BLOCK DIAGRAM ...............................................................................................................................15 PIN ASSIGNMENTS .........................................................................................................................................................16 5.1. 6. PIN ASSIGNMENT TABLE (208-PIN PQFP)..................................................................................................................17
PIN DESCRIPTIONS ........................................................................................................................................................19 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. 6.9. SMII INTERFACE (PORT #0 ~ PORT #23).....................................................................................................................19 TBI/GMII/MII INTERFACE (PORT #G0 ~ PORT #G1) .................................................................................................20 SERIAL MANAGEMENT INTERFACE (SMI) ..................................................................................................................24 SERIAL EEPROM INTERFACE ....................................................................................................................................25 SYSTEM PINS..............................................................................................................................................................25 MODE CONTROL PINS ................................................................................................................................................26 LED PINS...................................................................................................................................................................29 POWER/GROUND PINS................................................................................................................................................31 TEST PINS ..................................................................................................................................................................32
7.
FUNCTIONAL DESCRIPTION.......................................................................................................................................33 7.1. 7.1.1. 7.1.2. 7.2. 7.3. 7.4. 7.5. 7.6. 7.7. 7.8. 7.9. 7.10. 7.11. RESET ........................................................................................................................................................................33 Hardware Reset ....................................................................................................................................................33 Software Reset ......................................................................................................................................................33 MAC TO PHY INTERFACE..........................................................................................................................................33 FAST ETHERNET PORT (SMII INTERFACE) ..................................................................................................................33 GIGABIT ETHERNET PORTS (GMII/TBI/MII) .............................................................................................................33 GMII/MII/TBI SIGNAL MAPPING ..............................................................................................................................34 MAC ADDRESS TABLE SEARCH AND LEARNING ........................................................................................................35 MAC TABLE AGING FUNCTION..................................................................................................................................35 ILLEGAL FRAME FILTERING........................................................................................................................................35 802.1D RESERVED GROUP ADDRESSES FILTERING CONTROL ....................................................................................35 BACKOFF ALGORITHM ...............................................................................................................................................35 INTER-PACKET GAP....................................................................................................................................................35 iii Track ID: JATR-1076-21 Rev.2.1
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
RTL8326 Datasheet
7.12. 7.13. 7.13.1. 7.13.2. 7.14. 7.15. 7.16. 7.16.1. 7.16.2. 7.17. 7.18. 7.18.1. 7.18.2. 7.18.3. 7.18.4. 7.18.5. 7.19. 7.19.1. 7.19.2. 7.19.3. 7.19.4. 7.20. 7.21. 7.22. 7.22.1. 7.22.2. 7.22.3. 7.23. 7.24. 7.25. 7.26. 7.27. 7.28. 7.28.1. 7.29. BUFFER MANAGEMENT..............................................................................................................................................35 FLOW CONTROL.........................................................................................................................................................36 802.3x Pause Flow Control ..................................................................................................................................36 Half Duplex Back Pressure Flow Control ............................................................................................................36 BROADCAST STORM FILTERING CONTROL .................................................................................................................36 HEAD-OF-LINE BLOCKING PREVENTION ...................................................................................................................36 PORT TRUNKING AND FAULT RECOVERY SUPPORT .....................................................................................................37 Load Balancing ....................................................................................................................................................37 Trunk Fault Auto Recovery...................................................................................................................................37 IGMP SNOOPING SUPPORT.........................................................................................................................................38 VLAN FUNCTION ......................................................................................................................................................38 Port-based VLAN..................................................................................................................................................39 802.1Q Tag-based VLAN ......................................................................................................................................39 Ingress/Egress Filtering Control Parameters.......................................................................................................39 Leaky VLAN..........................................................................................................................................................40 Insert/Remove VLAN Priority Tag ........................................................................................................................40 QOS FUNCTION ..........................................................................................................................................................40 Port-Based Priority ..............................................................................................................................................41 802.1p/Q Based Priority.......................................................................................................................................41 Differentiated Service Based Priority...................................................................................................................41 Flow Control Auto Turn Off..................................................................................................................................42 INGRESS AND EGRESS BANDWIDTH CONTROL ...........................................................................................................42 SIMPLE MIB COUNTER SUPPORT ...............................................................................................................................42 RRCP(R) REALTEK REMOTE CONTROL PROTOCOL ......................................................................................................42 RRCP Capabilities................................................................................................................................................43 Management Security Scheme ..............................................................................................................................43 RRCP(R) Protocol Packet Format...........................................................................................................................44 NETWORK LOOP CONNECTION FAULT DETECTION.....................................................................................................46 REALTEK ECHO PROTOCOL ........................................................................................................................................47 PORT SECURITY CONTROL .........................................................................................................................................47 DISABLE PORT ...........................................................................................................................................................47 PORT PROPERTIES CONFIGURATION ...........................................................................................................................47 SERIAL CPU INTERFACE ............................................................................................................................................48 Serial-CPU Access Format ..................................................................................................................................49 PHY SERIAL MANAGEMENT INTERFACE ....................................................................................................................50 iv Track ID: JATR-1076-21 Rev.2.1
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RTL8326 Datasheet
7.29.1. 7.29.2. 7.30. 7.31. 7.32. 7.33. 7.33.1. 7.33.2. 8. SMI (MDC, MDIO) Interface ...............................................................................................................................51 PHY Register Indirect Access ...............................................................................................................................51 GENERAL PURPOSE I/O INTERFACE............................................................................................................................51 LED INTERFACES.......................................................................................................................................................51 PARALLEL LED INTERFACE........................................................................................................................................51 SERIAL LED INTERFACE ............................................................................................................................................52 Serial LED Display Panel Example (4 LEDs, Register 0x0005)..........................................................................53 Serial LED Shift Out Sequence Order ..................................................................................................................53
SERIAL EEPROM CONFIGURATION (24LC024) ......................................................................................................54 8.1. EEPROM CONFIGURATION VS. INTERNAL REGISTER MAPPING TABLE .....................................................................54
9.
INTERNAL REGISTER DESCRIPTIONS.....................................................................................................................55 9.1. 9.2. 9.3. 9.4. 9.5. 9.6. 9.7. 9.8. 9.8.1. 9.8.2. 9.8.3. 9.9. SYSTEM CONFIGURATION REGISTERS ........................................................................................................................55 SYSTEM STATUS REGISTERS.......................................................................................................................................56 MANAGEMENT CONFIGURATION REGISTERS..............................................................................................................56 ADDRESS LOOKUP TABLE (ALT) CONTROL REGISTER ...............................................................................................56 QUEUE CONTROL REGISTERS.....................................................................................................................................59 PHY ACCESS CONTROL REGISTER .............................................................................................................................59 PORT CONTROL REGISTERS........................................................................................................................................60 MIB COUNTER REGISTERS.........................................................................................................................................60 Port MIB Counter 1 Register (RX Counter) (32-bits) ..........................................................................................61 Port MIB Counter 2 Register (TX Counter) (32-bits)...........................................................................................62 Port MIB Counter 3 Register (Diagnostic Counter) (32-bits)..............................................................................63 SYSTEM PARAMETER REGISTER (RESERVED) .............................................................................................................63 INTERNAL REGISTER SETTINGS...........................................................................................................................64 SYSTEM CONFIGURATION REGISTER ..........................................................................................................................64 0x0000H: System Reset Control Register .............................................................................................................64 0x0001H: Switch Parameter Register ..................................................................................................................65 0x0002H: RX I/O PAD Delay Configuration........................................................................................................66 0x0003H: TX I/O PAD Delay Configuration ........................................................................................................67 0x0004H: General Purpose User Defined I/O Data Register ..............................................................................67 0X0005H: LED DISPLAY CONFIGURATION ................................................................................................................68 SYSTEM STATUS REGISTER.........................................................................................................................................69 0x0100H: Board Trapping Status Register...........................................................................................................69 0x0101H: Loop Detect Status Register (32-Bit Register) .....................................................................................69 v Track ID: JATR-1076-21 Rev.2.1
10.
10.1. 10.1.1. 10.1.2. 10.1.3. 10.1.4. 10.1.5. 10.2. 10.3. 10.3.1. 10.3.2.
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
RTL8326 Datasheet
10.3.3. 10.4. 10.4.1. 10.4.2. 10.4.3. 10.4.4. 10.4.5. 10.4.6. 10.4.7. 10.5. 10.6. 10.7. 10.8. 10.8.1. 10.9. 10.9.1. 10.9.2. 10.9.3. 10.9.4. 10.9.5. 10.9.6. 10.9.7. 10.9.8. 10.9.9. 10.9.10. 10.9.11. 10.9.12. 10.9.13. 10.10. 0x0102H: System Fault Indication Register.........................................................................................................70 MANAGEMENT CONFIGURATION REGISTER ...............................................................................................................71 0x0200H: Realtek Protocol Control Register.......................................................................................................71 0x0201H: RRCP Security Mask Configuration Register 0...................................................................................71 0x0202H: RRCP Security Mask Configuration Register 1...................................................................................71 0x0203H: Switch MAC ID Register 0...................................................................................................................72 0x0204H: Switch MAC ID Register 1...................................................................................................................72 0x0205H: Switch MAC ID Register 2...................................................................................................................72 0x0206H: Chip Model ID .....................................................................................................................................72 0X0207H: SYSTEM VENDER ID REGISTER 0 ..............................................................................................................72 0X0208H: SYSTEM VENDER ID REGISTER 1 ..............................................................................................................73 0X0209H: RRCP AUTHENTICATION KEY CONFIGURATION REGISTER .......................................................................73 0X020AH: PORT 0, 1 BANDWIDTH CONTROL REGISTER ............................................................................................73 0x020BH ~ 0x0216H: Port 2 ~ 25 Bandwidth Control Register ..........................................................................74 ADDRESS LOOKUP TABLE (ALT) CONTROL REGISTER ...............................................................................................75 0x0300H: ALT Configuration Register.................................................................................................................75 0x0301H: Address Learning Control Register 0 ..................................................................................................75 0x0302H: Address Learning Control Register 1 ..................................................................................................76 0x0303H: Unknown SA Capture Register 0 .........................................................................................................76 0x0304H: Unknown SA Capture Register 1 .........................................................................................................76 0x0305H: Unknown SA Capture Register 2 .........................................................................................................76 0x0306H: Unknown SA Status Register................................................................................................................77 0x0307H: Port Trunking Configuration Register .................................................................................................77 0x0308H: IGMP Snooping Control Register........................................................................................................78 0x0309H: IP Multicast Router Port Discovery Register (32 bits) ...................................................................78 0x030BH: VLAN Control Register...................................................................................................................78 0x030C~0x0318H: Port VLAN ID Assignment Index Register 0~12...............................................................79 0x0319~0x031CH: VLAN Output Port Priority-Tagging Control Register 0, 1, 2, 3 ......................................80
0X031D~0X037CH: VLAN TABLE CONFIGURATION REGISTERS ..............................................................................80 Register VLAN(m)_Entry_Configuration_0 (Addr: (0x031DH+3m)) .............................................................80 Register VLAN(m)_Entry_Configuration_1 (Addr: (0x031DH+3m+1)) ........................................................80 Register VLAN(m)_Entry_Configuration_2 (Addr: (0x031DH+3m+2)) ........................................................81
10.10.1. 10.10.2. 10.10.3. 10.11.
QOS CONFIGURATION REGISTER................................................................................................................................81 0x0400H: QoS Control Register ......................................................................................................................81 0x0401: Port Priority Configuration Registers 0 ............................................................................................82 vi Track ID: JATR-1076-21 Rev.2.1
10.11.1. 10.11.2.
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
RTL8326 Datasheet
10.11.3. 10.12. 0x0402: Port Priority Configuration Registers 1 ............................................................................................82
PHY ACCESS CONTROL REGISTER .............................................................................................................................82 0x0500H: PHY Access Control Register..........................................................................................................82 0x0501H: PHY Access Write Data Register ....................................................................................................83 0x0502H: PHY Access Read Data Register.....................................................................................................83
10.12.1. 10.12.2. 10.12.3. 10.13.
PORT CONTROL REGISTER..........................................................................................................................................83 0x0607H: Global Port Control Register..........................................................................................................83 0x0608H: Port Disable Control Register 0 .....................................................................................................84 0x0609H: Port Disable Control Register 1 .....................................................................................................84 0x060AH~0x0616. Port Property Configuration Register 0 ~ 12....................................................................85 0x0619H~0x0625. Port Link Status Register 0 ~ 12........................................................................................86
10.13.1. 10.13.2. 10.13.3. 10.13.4. 10.13.5. 11. 11.1. 11.2. 11.2.1. 11.2.2. 11.2.3. 12.
MIB COUNTER REGISTER .......................................................................................................................................88 0X0700H ~ 0X070CH: PORT MIB COUNTER OBJECT SELECTION REGISTER 0 ~ 12...................................................88 0X070DH ~0726H: PORT MIB COUNTER 1 REGISTER (RX COUNTER) (32 BITS) ......................................................89 For Port(n) MIB Counter 1 Register (32-bit). n=0, 1, 2, ... 25 (Addr: 0x070DH+n)..........................................90 0x0727~0740H: Port MIB Counter 2 Register (TX Counter) (32-bits)................................................................90 0x0741~075AH: Port MIB Counter 3 Register (Diagnostic Counter) (32-bits) ..................................................90
CHARACTERISTICS ...................................................................................................................................................91 ABSOLUTE MAXIMUM RATINGS.................................................................................................................................91 OPERATING RANGE ....................................................................................................................................................91 DC CHARACTERISTICS...............................................................................................................................................91 DIGITAL TIMING CHARACTERISTICS...........................................................................................................................92 PHY Management (SMI) Timing...........................................................................................................................92 SMII Transmit Timing...........................................................................................................................................93 SMII Receive Timing.............................................................................................................................................93 GMII Transmit Timing ..........................................................................................................................................94 GMII Receive Timing............................................................................................................................................94 MII Transmit Timing.............................................................................................................................................95 MII Receive Timing...............................................................................................................................................95 TBI Transmit Timing.............................................................................................................................................96 TBI Receive Timing...............................................................................................................................................96 THERMAL DATA .........................................................................................................................................................97
12.1. 12.2. 12.3. 12.4. 12.4.1. 12.4.2. 12.4.3. 12.4.4. 12.4.5. 12.4.6. 12.4.7. 12.4.8. 12.4.9. 12.5. 13.
MECHANICAL INFORMATION................................................................................................................................98 MECHANICAL DIMENSIONS NOTES ............................................................................................................................99 vii Track ID: JATR-1076-21 Rev.2.1
13.1.
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
RTL8326 Datasheet
List of Tables
TABLE 1. PIN ASSIGNMENTS (1 ~ 104).........................................................................................................................................17 TABLE 2. PIN ASSIGNMENTS (105 ~208) .....................................................................................................................................18 TABLE 3. SMII INTERFACE (PORT #0 ~ PORT #23) ......................................................................................................................19 TABLE 4. TBI/GMII/MII INTERFACE (PORT #G0 ~ PORT #G1)...................................................................................................20 TABLE 5. SERIAL MANAGEMENT INTERFACE (SMI)....................................................................................................................24 TABLE 6. SERIAL EEPROM INTERFACE......................................................................................................................................25 TABLE 7. SYSTEM PINS................................................................................................................................................................25 TABLE 8. MODE CONTROL PINS ..................................................................................................................................................26 TABLE 9. LED PINS .....................................................................................................................................................................29 TABLE 10. POWER/GROUND PINS .................................................................................................................................................31 TABLE 11. TEST PINS ....................................................................................................................................................................32 TABLE 12. GMII/MII/TBI SIGNAL MAPPING ................................................................................................................................34 TABLE 13. VLAN TABLE FORMAT ...............................................................................................................................................38 TABLE 14. PORT VLAN ID (PVID) ASSIGNMENT TABLE .............................................................................................................38 TABLE 15. MIB OBJECT SELECTION .............................................................................................................................................42 TABLE 16. HELLO/GET/SET/GET_REPLY PACKET FORMAT DESCRIPTION ....................................................................................44 TABLE 17. HELLO_REPLY PACKET FORMAT DESCRIPTION...........................................................................................................45 TABLE 18. GIGABIT PORT PAUSE ..................................................................................................................................................48 TABLE 19. CONFIGURING PAUSE AND ASYMMETRIC PAUSE .........................................................................................................48 TABLE 20. SMI (MDC, MDIO) MANAGEMENT PACKET FORMAT ................................................................................................51 TABLE 21. SERIAL LED INTERFACE..............................................................................................................................................52 TABLE 22. EEPROM CONFIGURATION VS. INTERNAL REGISTER MAPPING TABLE ......................................................................54 TABLE 23. SYSTEM CONFIGURATION REGISTERS..........................................................................................................................55 TABLE 24. SYSTEM STATUS REGISTERS ........................................................................................................................................56 TABLE 25. MANAGEMENT CONFIGURATION REGISTERS ...............................................................................................................56 TABLE 26. ADDRESS LOOKUP TABLE (ALT) CONTROL REGISTER................................................................................................56 TABLE 27. QUEUE CONTROL REGISTERS ......................................................................................................................................59 TABLE 28. PHY ACCESS CONTROL REGISTER ..............................................................................................................................59 TABLE 29. PORT CONTROL REGISTERS .........................................................................................................................................60 TABLE 30. MIB COUNTER REGISTERS ..........................................................................................................................................60 TABLE 31. PORT MIB COUNTER 1 REGISTER (RX COUNTER) (32-BITS) .......................................................................................61 TABLE 32. PORT MIB COUNTER 2 REGISTER (TX COUNTER) (32-BITS) .......................................................................................62 TABLE 33. PORT MIB COUNTER 3 REGISTER (DIAGNOSTIC COUNTER) (32-BITS).........................................................................63 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller viii Track ID: JATR-1076-21 Rev.2.1
RTL8326 Datasheet
TABLE 34. SYSTEM PARAMETER REGISTER (RESERVED) ..............................................................................................................63 TABLE 35. 0X0000H: SYSTEM RESET CONTROL REGISTER...........................................................................................................64 TABLE 36. 0X0001H: SWITCH PARAMETER REGISTER..................................................................................................................65 TABLE 37. 0X0002H: RX I/O PAD DELAY CONFIGURATION........................................................................................................66 TABLE 38. 0X0003H: TX I/O PAD DELAY CONFIGURATION........................................................................................................67 TABLE 39. 0X0004H: GENERAL PURPOSE USER DEFINED I/O DATA REGISTER............................................................................67 TABLE 40. 0X0005H: LED DISPLAY CONFIGURATION .................................................................................................................68 TABLE 41. 0X0100H: BOARD TRAPPING STATUS REGISTER .........................................................................................................69 TABLE 42. 0X0101H: LOOP DETECT STATUS REGISTER (32-BIT REGISTER).................................................................................69 TABLE 43. 0X0102H: SYSTEM FAULT INDICATION REGISTER.......................................................................................................70 TABLE 44. 0X0200H: REALTEK PROTOCOL CONTROL REGISTER..................................................................................................71 TABLE 45. 0X0201H: RRCP SECURITY MASK CONFIGURATION REGISTER 0 ...............................................................................71 TABLE 46. 0X0202H: RRCP SECURITY MASK CONFIGURATION REGISTER 1 ...............................................................................71 TABLE 47. 0X0203H: SWITCH MAC ID REGISTER 0.....................................................................................................................72 TABLE 48. 0X0204H: SWITCH MAC ID REGISTER 1.....................................................................................................................72 TABLE 49. 0X0205H: SWITCH MAC ID REGISTER 2.....................................................................................................................72 TABLE 50. 0X0206H: CHIP MODEL ID..........................................................................................................................................72 TABLE 51. 0X0207H: SYSTEM VENDER ID REGISTER 0 ................................................................................................................72 TABLE 52. 0X0208H: SYSTEM VENDER ID REGISTER 1 ................................................................................................................73 TABLE 53. 0X0209H: RRCP AUTHENTICATION KEY CONFIGURATION REGISTER ........................................................................73 TABLE 54. 0X020AH: PORT 0, 1 BANDWIDTH CONTROL REGISTER..............................................................................................73 TABLE 55. 0X020BH ~ 0X0216H: PORT 2 ~ 25 BANDWIDTH CONTROL REGISTER .......................................................................74 TABLE 56. 0X0300H: ALT CONFIGURATION REGISTER................................................................................................................75 TABLE 57. 0X0301H: ADDRESS LEARNING CONTROL REGISTER 0 ...............................................................................................75 TABLE 58. 0X0302H: ADDRESS LEARNING CONTROL REGISTER 1 ...............................................................................................76 TABLE 59. 0X0303H: UNKNOWN SA CAPTURE REGISTER 0 .........................................................................................................76 TABLE 60. 0X0304H: UNKNOWN SA CAPTURE REGISTER 1 .........................................................................................................76 TABLE 61. 0X0305H: UNKNOWN SA CAPTURE REGISTER 2 .........................................................................................................76 TABLE 62. 0X0306H: UNKNOWN SA STATUS REGISTER ..............................................................................................................77 TABLE 63. 0X0307H: PORT TRUNKING CONFIGURATION REGISTER .............................................................................................77 TABLE 64. 0X0308H: IGMP SNOOPING CONTROL REGISTER .......................................................................................................78 TABLE 65. 0X0309H: IP MULTICAST ROUTER PORT DISCOVERY REGISTER (32 BITS)..................................................................78 TABLE 66. 0X030BH: VLAN CONTROL REGISTER .......................................................................................................................78 TABLE 67. 0X030C~0X0318H: PORT VLAN ID ASSIGNMENT INDEX REGISTER 0~12.................................................................79 TABLE 68. 0X0319~0X031CH: VLAN OUTPUT PORT PRIORITY-TAGGING CONTROL REGISTER 0, 1, 2, 3 ...................................80 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller ix Track ID: JATR-1076-21 Rev.2.1
RTL8326 Datasheet
TABLE 69. REGISTER VLAN(M)_ENTRY_CONFIGURATION_0 (ADDR: (0X031DH+3M)) .............................................................80 TABLE 70. REGISTER VLAN(M)_ENTRY_CONFIGURATION_1 (ADDR: (0X031DH+3M+1)) .........................................................80 TABLE 71. REGISTER VLAN(M)_ENTRY_CONFIGURATION_2 (ADDR: (0X031DH+3M+2)) .........................................................81 TABLE 72. 0X0400H: QOS CONTROL REGISTER ...........................................................................................................................81 TABLE 73. 0X0401: PORT PRIORITY CONFIGURATION REGISTERS 0 .............................................................................................82 TABLE 74. 0X0402: PORT PRIORITY CONFIGURATION REGISTERS 1 .............................................................................................82 TABLE 75. 0X0500H: PHY ACCESS CONTROL REGISTER .............................................................................................................82 TABLE 76. 0X0501H: PHY ACCESS WRITE DATA REGISTER........................................................................................................83 TABLE 77. 0X0502H: PHY ACCESS READ DATA REGISTER .........................................................................................................83 TABLE 78. 0X0607H: GLOBAL PORT CONTROL REGISTER............................................................................................................83 TABLE 79. 0X0608H: PORT DISABLE CONTROL REGISTER 0 ........................................................................................................84 TABLE 80. 0X0609H: PORT DISABLE CONTROL REGISTER 1 ........................................................................................................84 TABLE 81. 0X060AH~0X0616. PORT PROPERTY CONFIGURATION REGISTER 0 ~ 12....................................................................85 TABLE 82. 0X0619H~0X0625. PORT LINK STATUS REGISTER 0 ~ 12............................................................................................86 TABLE 83. 0X0700H ~ 0X070CH: PORT MIB COUNTER OBJECT SELECTION REGISTER 0 ~ 12 ....................................................88 TABLE 84. MIB COUNTER TIMEOUT .............................................................................................................................................89 TABLE 85. 0X070DH ~0726H: PORT MIB COUNTER 1 REGISTER (RX COUNTER) (32 BITS) ........................................................90 TABLE 86. 0X0727~0740H: PORT MIB COUNTER 2 REGISTER (TX COUNTER) (32 BITS).............................................................90 TABLE 87. 0X0741~075AH: PORT MIB COUNTER 3 REGISTER (DIAGNOSTIC COUNTER) (32 BITS) .............................................90 TABLE 88. ELECTRICAL CHARACTERISTICS/RATINGS...................................................................................................................91 TABLE 89. DC CHARACTERISTICS.................................................................................................................................................91 TABLE 90. PHY MANAGEMENT (SMI) TIMING.............................................................................................................................92 TABLE 91. PHY MANAGEMENT (SMI) TIMING.............................................................................................................................93 TABLE 92. SMII RECEIVE TIMING.................................................................................................................................................93 TABLE 93. GMII TRANSMIT TIMING .............................................................................................................................................94 TABLE 94. GMII RECEIVE TIMING ................................................................................................................................................94 TABLE 95. MII TRANSMIT TIMING ................................................................................................................................................95 TABLE 96. MII RECEIVE TIMING...................................................................................................................................................95 TABLE 97. TBI TRANSMIT TIMING................................................................................................................................................96 TABLE 98. TBI RECEIVE TIMING...................................................................................................................................................96 TABLE 99. THERMAL OPERATING RANGE .....................................................................................................................................97 TABLE 100. THERMAL RESISTANCE ..............................................................................................................................................97
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List of Figures
FIGURE 1. BLOCK DIAGRAM........................................................................................................................................................14 FIGURE 2. FUNCTIONAL BLOCK DIAGRAM ..................................................................................................................................15 FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................16 FIGURE 4. 802.1Q VLAN TAG FRAME FORMAT..........................................................................................................................41 FIGURE 5. IPV4 FRAME FORMAT .................................................................................................................................................41 FIGURE 6. IPV6 FRAME FORMAT .................................................................................................................................................41 FIGURE 7. REALTEK REMOTE CONTROL PROTOCOL ....................................................................................................................43 FIGURE 8. HELLO/GET/SET/GET_REPLY PACKET FORMAT .........................................................................................................44 FIGURE 9. HELLO_REPLY PACKET FORMAT ................................................................................................................................45 FIGURE 10. LOOP DETECT PACKET FORMAT.................................................................................................................................46 FIGURE 11. REALTEK ECHO PROTOCOL FRAME ............................................................................................................................47 FIGURE 12. SERIAL CPU INTERFACE.............................................................................................................................................48 FIGURE 13. START AND STOP DEFINITION.....................................................................................................................................49 FIGURE 14. OUTPUT ACKNOWLEDGE (ACK) ................................................................................................................................49 FIGURE 15. SERIAL CPU 16-BIT READ/WRITE FORMAT ...............................................................................................................50 FIGURE 16. SERIAL CPU 32-BIT READ/WRITE FORMAT ...............................................................................................................50 FIGURE 17. SERIAL LED DISPLAY ................................................................................................................................................53 FIGURE 18. MDC/MDIO WRITE TIMING ......................................................................................................................................92 FIGURE 19. MDC/MDIO READ TIMING........................................................................................................................................92 FIGURE 20. MDC/MDIO RESET TIMING.......................................................................................................................................92 FIGURE 21. SMII TRANSMIT TIMING.............................................................................................................................................93 FIGURE 22. SMII RECEIVE TIMING ...............................................................................................................................................93 FIGURE 23. GMII TRANSMIT TIMING ............................................................................................................................................94 FIGURE 24. GMII RECEIVE TIMING...............................................................................................................................................94 FIGURE 25. MII TRANSMIT TIMING...............................................................................................................................................95 FIGURE 26. MII RECEIVE TIMING..................................................................................................................................................95 FIGURE 27. TBI TRANSMIT TIMING...............................................................................................................................................96 FIGURE 28. TBI RECEIVE TIMING .................................................................................................................................................96 FIGURE 29. CROSS-SECTION OF 208 PQFP ....................................................................................................................................97
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1.
General Description
The RTL8326 is a layer-2 switch controller that integrates 2.5Mbits of high-speed SSRAM, an 8K-entry MAC address lookup table, 24 Ethernet/Fast Ethernet MACs, two Gigabit Ethernet MACs, and a switch engine into one chip. The Remote Management Tool (RMT) software package is bundled with the RTL8326. The RMT is a Windows-based tool developed to enhance the functionality of Realtek's dumb layer 2 switches via software. The RMT gives network administrators the ability to remotely configure and monitor dumb layer 2 switches as though they were intelligent switches. With QoS, Trunking, VLAN, bandwidth control, remote control, and an 0.18m process, the RTL8326 is a cost effective switch controller for a 24+2G dumb or smart switch application. Port trunking is supported on all ports to increase bandwidth. Load balancing and fault tolerance provide top performance and reliability. The RTL8326 provides 2-level priority queues for multimedia or realtime network applications. The CoS (Class of Service) can be port-based, IEEE 802.1p tag-based, and/or TCP/IP header TOS/DS field based. The RTL8326 supports up to 32 VLAN groups that may be configured as port-based VLANs and/or IEEE 802.1Q tagged VLANs. ARP broadcast and Leaky VLAN are also supported. The RTL8326 features a built-in PCS (Physical Coding Sublayer) to support a SERDES (serializer/deserializer) transceiver for Gigabit fiber applications. For diagnostics/analysis, RX byte count, RX packet count, TX byte count, TX packet count, CRC error packet count, collision packet count, drop packet count, and drop byte counters are included. The RTL8326 supports TX and RX bandwidth control on each port. 128Kbps, 256Kbps, 512kbps, 1Mbps, 2Mbps, 4Mbps, and 8Mbps may be selected in each direction. A loop-detection function is provided to notify if a network loop exists, either via a visual LED, or via a register flag for smart applications. LED displays for broadcast storm, trunking status, flow control, and traffic utilization are also provided. Maximum packet length can be up to 1552 bytes. A filtering function of the 802.1D specified reserved group MAC addresses according to pin strapping upon reset or register setting is supported for flexible proprietary applications. The RTL8326 supports IEEE 802.3x full duplex flow control and back pressure half duplex flow control. Full duplex flow control can be disabled manually or automatically to ensure QoS control or bandwidth control works correctly. Broadcast storm filtering prevents network crashes caused by abnormal broadcast activity. As well as supporting 802.3u auto-negotiation, the RTL8326 supports PHY Read/Write registers to access PHY registers through an MDC/MDIO interface. This expands system configuration options. Inband management of the functions provided by the RTL8326 may be implemented using a simple 8051 microprocessor, or via the RTL8326's RRCP(R) protocol based Remote Management Tool (RMT). The RTL8326 is designed with a link-list buffer management architecture and provides 8.8Gbps of bandwidth to achieve wire-speed performance. It also has an intelligent switching engine to prevent Head-of-Line blocking. Only a single 25MHz crystal is required for clock generation.
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
12
Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
2.
Features
24 10/100Mbps + 2 10/100/1000Mbps port layer-2 Ethernet switch controller with embedded lookup table and packet buffer Supports SMII on 10/100Mbps ports Supports MII, GMII, or TBI on Giga-ports Complies with 802.3z and 802.3ab Half/full duplex for MII Full duplex for GMII/TBI Built-in PCS for SERDES transceiver Built-in 8K entry MAC address lookup table plus 64-entry CAM to eliminate hash collision problems Built-in 2.5Mbit SSRAM packet buffer Non-blocking wire-speed forwarding and filtering (8.8Gbps throughput) Store and forward architecture and head-ofline blocking prevention All ports support Speed, Duplex, and 802.3x flow-control ability auto-negotiation Supports broadcast storm filtering control Supports 802.3x full duplex flow control and back pressure half duplex flow control Supports Trunking function with load balancing and fault tolerance for 10/100M ports and Gigabit ports Supports up to 32 VLAN groups for portbased VLAN and 802.1Q tag VLAN Supports Leaky VLAN Two priority queues for three types of Class of Service (CoS) Port- based 802.1p priority tag TCP/IP header's TOS/DS classifier Weighted round robin queue scheduling Priority tag insert and remove function Supports ASIC based IGMP snooping function Supports pin strapping, EEPROM, or serial CPU configuration interface Supports PHY register read/write access Supports Realtek Remote Control Protocol (RRCP(R)) for in-band configuration and management Supports SMII/GMII interface I/O delay control Supports simple MIB counters TX/RX packet/byte, CRC error, and collision counter for diagnostics/statistics Supports per-port bandwidth control Supports loop detection and indication function Provides serial LED and parallel LED interface for port properties and diagnostic display Needs only one low cost 25MHz crystal or OSC input 0.18m, 208-pin PQFP, 3.3V single power, 5V I/O tolerance
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
13
Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
3.
Block Diagram
RTL8326 system architecture
Dumb/Smart
Out band control
8051
25MHz Crystal
GMII
Realtek RTL8326
SMII
Giga-PHY Giga-PHY
EEPROM
Octal-PHY (RTL8208)
Octal-PHY (RTL8208)
Octal-PHY (RTL8208)
TXR x 4
TXR x 4
TXR x 4
TXR x 4
TXR x 4
TXR x 4
RJ45 x 4
RJ45 x 4
RJ45 x 4
RJ45 x 4
RJ45 x 4
RJ45 x 4
In band control
10/100Mbps x 24 + 10/100/1000M x 2
Copyright (c) 2002 Realtek Sem iconductor Corp. www.realtek.com .tw
Figure 1. Block Diagram
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
14
Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
4.
Functional Block Diagram
24 Ports
2 Ports GMII/ TBI/ MII
PHY Management I/F
EEPROM I/F
LED I/F
SMII
10/100 MAC
Buffer Management 10/100/1000 MAC DMA Engine
RX FIFO
TX FIFO
RX FIFO
TX FIFO Packet Buffer
TX Start Addr. Queue
TX Start Addr. Queue Switching Engine
Flow Control
Flow Control
8K-Entry Address Table Internal CAM for Address Lookup Address Lookup Engine
Figure 2. Functional Block Diagram
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
15
Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
5.
Pin Assignments
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
EnExt18VPwr VDD0 RVDD0 GND P0TXD/FrcTBIMode[0] P0RXD P1TXD/FrcTBIMode[1] P1RXD P2TXD/MaxPktLen[0] P2RXD DVDD DGND P3TXD/MaxPktLen[1] P3RXD SYNC_0_7 P4TXD/TXIPG_Comp P4RXD P5TXD/MaxPauseCnt P5RXD P6TXD/DisBKP48One P6RXD DVDD DGND VDD0 GND P7TXD/EnGDSRev P7RXD REFCLK_0_7 P8TXD P8RXD P9TXD/EnLoopDet P9RXD DVDD DGND P10TXD/DisRRCP P10RXD P11TXD/DisREcho P11RXD SYNC_8_15 P12TXD/EnFastAgeTime P12RXD P13TXD/EnCtrlFFilter P13RXD DVDD DGND P14TXD/EnIGMPsnooping P14RXD GND VDD1 RVDD1 P15TXD/EnHomeVLAN P15RXD
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
VDD3 GND G1RXD[5] G1RXD[6] G1RXD[7] LED_DMODE_CK LED_GLink/ACT[1] LED_GLink/ACT[0] Reserved(VLED) LED_LoopDet DVDD DGND LED_BISTFail LED_EnTrunk[7] LED_EnTrunk[6] LED_EnTrunk[5] LED_EnTrunk[4] LED_EnTrunk[3] LED_EnTrunk[2] LED_EnTrunk[1]/SLED_DATA LED_EnTrunk[0]/SLED_CLK RST# VDD0 GND DVDD USR_IO[3] USR_IO[2] USR_IO[1] USR_IO[0] EnTESTMODE TEST_IOWPS TEST_IORPS TEST_PS TEST_IOA[5] TEST_IOA[4] TEST_IOA[3] TEST_IOA[2] TEST_IOA[1] TEST_IOA[0] TEST_IOE TEST_IOD[7] TEST_IOD[6] TEST_IOD[5] TEST_IOD[4] DVDD DGND TEST_IOD[3] TEST_IOD[2] TEST_IOD[1] TEST_IOD[0] SCK SDA
RVDD3 G1RXD[4] G1RXD[3] G1RXD[2] G1RXD[1] G1RXD[0] G1RX_DV/G1RXDS[8] DGND DVDD G1RX_CLK/G1RSCK0 G1RXDS[9] G1COL G1CRS G1RSCK1/G1TXC G1TXDS[9] G1TX_CLK G1TX_EN/G1TXDS[8]/EnCRSBKPmode GND VDD3 DGND DVDD G1TXD[0] G1TXD[1] G1TXD[2] G1TXD[3] G1TXD[4] G1TXD[5] G1TXD[6] G1TXD[7] DGND DVDD G1_25MCKO G0RXD[7] G0RXD[6] G0RXD[5] G0RXD[4] G0RXD[3] G0RXD[2] G0RXD[1] Ext125CLKI EnExt125CLK ExtSysCLKI EnExtSysCLK AVDD2 AVSS2 XO XI/OSCI AVSS1 AVDD1 GND RVDD2 VDD2
RTL8326
G0RXD[0] G0RX_DV/G0RXDS[8] G0RX_CLK/G0RSCK0 G0RXDS[9] G0COL G0CRS G0RSCK1/G0TXC G0TXDS[9] G0TX_CLK DGND DVDD G0TX_EN/G0TXDS[8]/DisBKP GND VDD2 G0TXD[0] G0TXD[1] G0TXD[2]/EnAcceptErr G0TXD[3]/TBI_G0_Force_Link DGND DVDD G0TXD[4]/TBI_G1_Force_Link G0TXD[5]/DisBRDCTRL G0TXD[6]/DisIPMCFC G0TXD[7]/DisBCFC MDIO MDC G0_25MCKO REFCLK_16_23 DGND DVDD P23RXD P23TXD/DisFDFC P22RXD P22TXD/PortPriSet[1] P21RXD P21TXD/PortPriSet[0] P20RXD P20TXD/QWEIGHT[1] SYNC_16_23 GND VDD1 P19RXD P19TXD/QWEIGHT[0] DGND DVDD P18RXD P18TXD/EnFCAutoOff P17RXD P17TXD/En8021pPri P16RXD P16TXD/EnDSPri REFCLK_8_15
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
Figure 3. Pin Assignments
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Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
5.1. Pin Assignment Table (208-Pin PQFP)
Type codes used: P = Power; G = Ground, I = Input, O = Output.
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Signal Name
EnExt18VPwr VDD0 RVDD0 GND P0TXD/(FrcTBIMode[0]) P0RXD P1TXD/(FrcTBIMode[1]) P1RXD P2TXD/(MaxPktLen[0]) P2RXD DVDD DGND P3TXD/( MaxPktLen[1]) P3RXD SYNC_0_7 P4TXD/(TXIPG_Comp) P4RXD P5TXD/(MaxPauseCnt) P5RXD P6TXD/(DisBKP48One) P6RXD DVDD DGND VDD0 GND P7TXD/(EnGDSRev) P7RXD REFCLK_0_7 P8TXD P8RXD P9TXD/(EnLoopDet) P9RXD DVDD DGND P10TXD/(DisRRCP) P10RXD P11TXD/(DisREcho) P11RXD SYNC_8_15 P12TXD/(EnFastAgeTime) P12RXD P13TXD/(EnCtrlFFilter) P13RXD DVDD DGND P14TXD/(EnIGMPsnooping) P14RXD GND VDD1 RVDD1 P15TXD/(EnHomeVLAN) P15RXD
Table 1. Pin Assignments (1 ~ 104) Type Pin # Signal Name
I P P G O I O I O I P G O I O O I O I O I P G P G O I O O I O I P G O I O I O O I O I P G O I G P P O I 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 REFCLK_8_15 P16TXD/(EnDSPri) P16RXD P17TXD/(En8021pPri) P17RXD P18TXD/(EnFCAutoOff) P18RXD DVDD DGND P19TXD/(QWEIGHT[0]) P19RXD VDD1 GND SYNC_16_23 P20TXD/(QWEIGHT[1]) P20RXD P21TXD/(PortPriSet[0]) P21RXD P22TXD/(PortPriSet[1]) P22RXD P23TXD/(DisFDFC) P23RXD DVDD DGND REFCLK_16_23 G0_25MCKO MDC MDIO G0TXD[7]/(DisBCFC) G0TXD[6]/(DisIPMCFC) G0TXD[5]/(DisBRDCTRL) G0TXD[4]/(TBI_G1_Force_Link) DVDD DGND G0TXD[3]/(TBI_G0_Force_Link) G0TXD[2]/(EnAcceptErr) G0TXD[1]/(DisTXCRCGen) G0TXD[0]/(EnSpdBkOff) VDD2 GND G0TX_EN/G0TXDS[8] /(DisBKP) DVDD DGND G0TX_CLK G0TXDS[9]/(EnSPDUP) G0RSCK1/G0TXC G0CRS G0COL G0RXDS[9] G0RX_CLK/G0RSCK0 G0RX_DV/G0RXDS[8] G0RXD[0]
Type
O O I O I O I P G O I P G O O I O I O I O I P G O O O IO O O O O P G O O O O P G O P G O O I I I I I I I
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
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Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
Pin #
105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Signal Name
Table 2. Pin Assignments (105 ~208) Type Pin # Signal Name
P P G P P I O P P I I I I I I I I I I I O P G O O O O O O O O P G P G O O O I I I I I P G I I I I I I P 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 VDD3 GND G1RXD[5] G1RXD[6] G1RXD[7] LED_DMODE_CK LED_GLink/ACT[1] LED_GLink/ACT[0] Reserved (VLED) LED_LoopDet DVDD DGND LED_BISTFail LED_EnTrunk[7] LED_EnTrunk[6] LED_EnTrunk[5] LED_EnTrunk[4] LED_EnTrunk[3] LED_EnTrunk[2] LED_EnTrunk[1]/SLED_DATA LED_EnTrunk[0]/ SLED_CLK RST# VDD0 GND DVDD USR_IO[3] USR_IO[2] USR_IO[1] USR_IO[0] EnTESTMODE TEST_IOWPS TEST_IORPS TEST_PS TEST_IOA[5] TEST_IOA[4] TEST_IOA[3] TEST_IOA[2] TEST_IOA[1] TEST_IOA[0] TEST_IOE TEST_IOD[7] TEST_IOD[6] TEST_IOD[5] TEST_IOD[4] DVDD DGND TEST_IOD[3] TEST_IOD[2] TEST_IOD[1] TEST_IOD[0] SCK SDA
Type
P G I I I O O O O O P G O O O O O O O O O I P G P I I I I I IO IO IO IO IO IO IO IO IO IO IO IO IO IO P G IO IO IO IO IO IO
VDD2 RVDD2 GND AVDD1 AVSS1 XI/OSCI XO AVSS2 AVDD2 EnExtSysCLK ExtSysCLKI EnExt125CLK Ext125CLKI G0RXD[1] G0RXD[2] G0RXD[3] G0RXD[4] G0RXD[5] G0RXD[6] G0RXD[7] G1_25MCKO DVDD DGND G1TXD[7] G1TXD[6] G1TXD[5] G1TXD[4] G1TXD[3] G1TXD[2] G1TXD[1] G1TXD[0] DVDD DGND VDD3 GND G1TX_EN/G1TXDS[8]/(EnCRSBKPmode) G1TX_CLK G1TXDS[9] G1RSCK1/G1TXC G1CRS G1COL G1RXDS[9] G1RX_CLK/G1RSCK0 DVDD DGND G1RX_DV/G1RXDS[8] G1RXD[0] G1RXD[1] G1RXD[2] G1RXD[3] G1RXD[4] RVDD3
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
18
Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
6.
Pin Descriptions
Type codes used: P = Power; G = Ground, I = Input, O = Output, Pu = Internal pull up (75K ohm), Pd = Internal pull down (75K ohm).
6.1. SMII Interface (Port #0 ~ Port #23)
Symbol P0TXD P1TXD P2TXD P3TXD P4TXD P5TXD P6TXD P7TXD P8TXD P9TXD P10TXD P11TXD P12TXD P13TXD P14TXD P15TXD P16TXD P17TXD P18TXD P19TXD P20TXD P21TXD P22TXD P23TXD Type O Table 3. SMII Interface (Port #0 ~ Port #23) Pin No. Description SMII Transmit Data Output: 5 SMII transmit data is formed in 10-bit serial words. Each word contains one 7 data byte (two nibbles of 4B coded data) and two 9 status bits. 13 The SMII operates at 125MHz using a global reference clock 16 (REFCLK) and frame synchronization signal (SYNC). 18 20 SMII transmit data is input on these pins, where: 26 Ports 0~7 transmit data is sent synchronously to SYNC_0_7 29 and REFCLK_0_7. 31 Ports 8~15 transmit data is sent synchronously to SYNC_8_15 35 and REFCLK_8_15. 37 Ports 16~23 transmit data is sent synchronously to SYNC_16_23 and 40 REFCLK_16_23. 42 46 51 54 56 58 62 67 69 71 73
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
19
Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
Symbol P0RXD P1RXD P2RXD P3RXD P4RXD P5RXD P6RXD P7RXD P8RXD P9RXD P10RXD P11RXD P12RXD P13RXD P14RXD P15RXD P16RXD P17RXD P18RXD P19RXD P20RXD P21RXD P22RXD P23RXD SYNC_0_7 SYNC_8_15 SYNC_16_23 Type I Pin No. 6 8 10 14 17 19 21 27 30 32 36 38 41 43 47 52 55 57 59 63 68 70 72 74 15 39 66 Description SMII Receive Data Input: SMII receive data is input on these pins. Where ports 0~7 receive data is received synchronously to SYNC_0_7 and REFCLK_0_7. Ports 8~15 receive data is received synchronously to SYNC_8_15 and REFCLK_8_15. Ports 16~23 receive data is received synchronously to SYNC_16_23 and REFCLK_16_23.
O
REFCLK_0_7 REFCLK_8_15 REFCLK_16_23
O
28 53 77
SMII Synchronization Output. SMII transmit/receive data 10-bit word frame synchronization. Where: SYNC_0_7 synchronizes data for ports 0~7. SYNC_8_15 synchronizes data for ports 8~15. SYNC_16_23 synchronizes data for ports 16~23. SMII Reference Clock Output. The SMII reference clock output is a 125MHz +- 50ppm clock used to synchronize the SMII data. Ports 0~7 data is sent or received synchronously to SYNC_0_3. Ports 8~15 data is sent or received synchronously to SYNC_8_15. Ports 16~23 data is sent or received synchronously to SYNC_16_23.
6.2. TBI/GMII/MII Interface (Port #G0 ~ Port #G1)
Symbol G0TX_CLK Mode TBI Table 4. TBI/GMII/MII Interface (Port #G0 ~ Port #G1) Type Pin No. Description O 96 Gigabit port Transmit Clock Output (TBI mode). 125Mhz transmit 8B/10B encoded code-group clock. Transmit Clock Output (GMII mode). 125MHz transmit clock used for G0_TXD synchronization.
G0TX_CLK Not Used
GMII MII
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
20
Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
Symbol G0TXDS[3:0] Mode TBI Type O Pin No. 87 88 89 90 Description Transmit Data Output (TBI mode). Transmits 8B/10B code group data synchronously to the rising edge of G0_TXCLK. Transmit Data Output (GMII mode). Transmits data synchronously to the rising edge of G0_TXCLK. Transmit Data Output (MII mode). Transmits data synchronously to the rising edge of G0_TXC. Transmit Data Output (TBI mode). Transmits 8B/10B code group data synchronously to the rising edge of G0_TXCLK. Transmit Data Output (GMII mode). Transmits data synchronously to the rising edge of G0_TXCLK. O 93 Transmit Data Output, bit[8] (TBI mode). Transmits 8B/10B code group data synchronously to the rising edge of G0_TXCLK. Transmit Enable Output (GMII mode). Transmit enable which is sent synchronously to the rising edge of G0_TXCLK. Transmit Enable Output (MII mode). Transmit enable which is sent synchronously to the rising edge of G0_TXC. Transmit Data Output, bit[9] (TBI mode). Transmits 8B/10B code group data synchronously to the rising edge of G0_TXCLK. Keep logic low level (GMII, MII) I 102 Receive Clock 0 Input (TBI mode). 62.5MHz receive clock. Used to latch odd numbered code-group data G0_TXDS in the received PHY bit stream. Receive Clock Input (GMII modes). 125Mhz receive clock. Used to synchronize received G0_TXD data. Receive Clock Input (MII modes). 2.5/25 MHz (10Mbps/100Mbps) receive clock. Used to synchronize received G0_RXD data. Receive Clock 1 Input (TBI mode). 62.5MHz receive clock. Used to latch even numbered code-group data in the received PHY bit stream.
G0TXD[3:0]
GMII
G0TD[3:0] G0TXDS[7:4]
MII TBI O 81 82 83 84
G0TXD[7:4] Not Used G0TXDS[8]
GMII MII TBI
G0TX_EN
GMII
G0TX_EN
MII
G0TXDS[9]
TBI
O
97
Not Used Not Used G0RSCK0
GMII MII TBI
G0RX_CLK
GMII
G0RXC
MII
G0RSCK1
TBI
I
98
Leave Unconnected G0TXC
GMII
MII
Transmit Clock Input (MII modes). 2.5/25 MHz (10Mbps/100Mbps) receive clock. The transmit data is sent synchronously on the rising edge of G0_TXC.
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
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Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
Symbol G0RXDS[3:0] Mode TBI Type I Pin No. 120 119 118 104 Description Receive Data Input (TBI mode). Receives 8B/10B code group data synchronously at the rising edge of G0_RXCLK. Receive Data Input (GMII mode). Receive data that is received synchronously at the rising edge of G0_RXCLK. Receive Data Input (MII mode). Receive data that is received synchronously at the rising edge of G0_RXC. Receive Data Input (TBI mode). Receives 8B/10B code group data synchronously at the rising edge of G0_RXCLK. Receive Data Input (GMII mode). Receive data that is received synchronously at the rising edge of G0_RXCLK. I 103 Receive Data Input (TBI mode). Receives 8B/10B code group data synchronously at the rising edge of G0_RXCLK. Receive Data Valid Input (GMII mode). Receive data valid that is received synchronously at the rising edge of G0_RXCLK. Receive Data Valid Input (MII mode). Receive data valid that is received synchronously at the rising edge of G0_RXC. Receive Data Input bit[9] (TBI mode). Receives 8B/10B code group data synchronously at the rising edge of G0_RXCLK. Carrier Sense Input (MII mode). G0CRS is only valid in MII half duplex mode. It is asserted high when a valid carrier is detected on the media. Collision Detect Input (MII). G0COL is only valid in MII half duplex mode. It is asserted high when a collision is detected on the media. Gigabit port Transmit Clock Output (TBI mode). 125Mhz transmit 8B/10B encoded code-group clock. Transmit Clock Output (GMII mode). 125MHz transmit clock used for G1_TXD synchronization.
G0RXD[3:0]
GMII
G0RXD[3:0]
MII
G0RXDS[7:4]
TBI
I
124 123 122 121
G0RXD[7:4]
GMII
Not Used G0RXDS[8]
MII TBI
G0RX_DV
GMII
G0RX_DV
MII
G0RXDS[9] Not Used Not Used Not Used Not Used G0CRS Not Used Not Used G0COL G1TX_CLK
TBI GMII MII TBI GMII MII TBI GMII MII TBI
I
101
I
99
I
100
O
141
G1TX_CLK Not Used
GMII MII
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
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Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
Symbol G1TXDS[3:0] Mode TBI Type O Pin No. 132 133 134 135 Description Transmit Data Output (TBI mode). Transmits 8B/10B code group data synchronously at the rising edge of G1_TXCLK. Transmit Data Output (GMII mode). Transmit data that is sent synchronously at the rising edge of G1_TXCLK. Transmit Data Output (MII mode). Transmit data that is sent synchronously at the rising edge of G1_TXC. Transmit Data Output (TBI mode). Transmits 8B/10B code group data synchronously at the rising edge of G1_TXCLK. Transmit Data Output (GMII mode). Transmit data that is sent synchronously at the rising edge of G1_TXCLK. Transmit Data Output, bit[8] (TBI mode). Transmits 8B/10B code group data synchronously at the rising edge of G1_TXCLK. Transmit Enable Output (GMII mode). Transmit enable that is sent synchronously at the rising edge of G1_TXCLK. Transmit Enable Output (MII mode). Transmit enable that is sent synchronously at the rising edge of G1_TXC. O 142 Transmit Data Output, bit[9] (TBI mode). Transmits 8B/10B code group data synchronously at the rising edge of G1_TXCLK. Keep logic low level (GMII, MII) I 147 Receive Clock 0 Input (TBI mode). 62.5MHz receive clock. Used to latch odd numbered code-group data G1_TXDS in the received PHY bit stream. Receive Clock Input (GMII modes). 125Mhz receive clock. Used to synchronize G1_TXD received data. Receive Clock Input (MII modes). 2.5/25 MHz (10Mbps/100Mbps) receive clock. Used to synchronize G1_RXD received data. Receive Clock 1 Input (TBI mode). 62.5MHz receive clock. Used to latch even numbered code-group data in the received PHY bit stream.
G1TXD[3:0]
GMII
G1TD[3:0]
MII
G1TXDS[7:4]
TBI
O
128 129 130 131
G1TXD[7:4] Not Used G1TXDS[8]
GMII MII TBI
O
140
G1TX_EN
GMII
G1TX_EN
MII
G1TXDS[9]
TBI
Not Used Not Used G1RSCK0
GMII MII TBI
G1RX_CLK
GMII
G1RXC
MII
G1RSCK1
TBI
I
143
Leave Unconnected G1TXC
GMII
MII
Transmit Clock Input (MII modes). 2.5/25 MHz (10Mbps/100Mbps) receive clock. The transmit data is sent synchronously at the rising edge of G1_TXC. 23 Track ID: JATR-1076-21 Rev. 2.1
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RTL8326 Datasheet
Symbol G1RXDS[3:0] Mode TBI Type I Pin No. 154 153 152 151 Description Receive Data Input (TBI mode). Receives 8B/10B code group data synchronously at the rising edge of G1_RXCLK. Receive Data Input (GMII mode). Receive data that is received synchronously at the rising edge of G1_RXCLK. Receive Data Input (MII mode). Receive data that is received synchronously at the rising edge of G1_RXC. Receive Data Input (TBI mode). Receives 8B/10B code group data synchronously at the rising edge of G1_RXCLK. Receive Data Input (GMII mode). Receive data that is received synchronously at the rising edge of G1_RXCLK.
G1RXD[3:0]
GMII
G1RXD[3:0]
MII
G1RXDS[7:4]
TBI
I
161 160 159 155
G1RXD[7:4]
GMII
Not Used G1RXDS[8]
MII TBI
I
150
Receive Data Input (TBI mode). Receives 8B/10B code group data synchronously at the rising edge of G1_RXCLK. Receive Data Valid Input (GMII mode). Receive data valid that is received synchronously at the rising edge of G1_RXCLK. Receive Data Valid Input (MII mode). Receive data valid that is received synchronously at the rising edge of G1_RXC. Receive Data Input bit[9] (TBI mode). Receive 8B/10B code group data that is received synchronously at the rising edge of G1_RXCLK. Carrier Sense Input (MII mode). G1CRS is only valid in MII half duplex mode. It is asserted high when a valid carrier is detected on the media. Collision Detect Input (MII). G1COL is only valid in MII half duplex mode. It is asserted high when a collision is detected on the media.
G1RX_DV
GMII
G1RX_DV
MII
G1RXDS[9] Not Used Not Used Not Used Not Used G1CRS Not Used Not Used G1COL
TBI GMII MII TBI GMII MII TBI GMII MII
I
146
I
144
I
145
6.3. Serial Management Interface (SMI)
Symbol MDC Type O (Pu) IO (Pu) Table 5. Serial Management Interface (SMI) Pin No Description 79 Serial Management Data Clock (MDC). MDC operates at 1MHz. MDC is in tri-state when RST# is active low. 80 Serial Management Data Input/Output. MDIO is in tri-state when RST# is active low.
MDIO
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6.4. Serial EEPROM Interface
Symbol SCK Type IO (Pu) Table 6. Serial EEPROM Interface Pin No Description 207 Serial EEPROM interface Clock Output/ Serial CPU Access Clock Input. SCLK acts as an output pin after hardware reset for EEPROM read access. When the configuration download from EEPROM is finished, or if the EEPROM does not exist, then the SCLK will act as an input pin driven by an external CPU to access the RTL8326 internal registers. SCLK Frequency: Output: Operates at 100KHz Input: Max limit: 10MHz 208 Serial EEPROM Data Input/Output/Serial CPU Access Data Input/Output. After power on, this pin is EEPROM serial data IO. When the configuration download from EEPROM is finished, or if the EEPROM does not exist, then this pin acts as a serial CPU data IO. See 7.28 Serial CPU Interface, page 48 for detailed data access format and timing information.
SDA
IO (Pu)
6.5. System Pins
Symbol RST# Type I (Pu) Pin No 178 Table 7. System Pins Description System Reset. Active low to reset the system to a known state. After power-on reset (low to high), the configuration modes from Mode Control Pins (page 26) are strapped and determined. Crystal Input/Oscillator Input. This is a 25Mhz +-50 ppm crystal input or oscillator input. When crystal is used, a capacitor connected from this pin to ground is recommended. Crystal Output. When crystal is used, a capacitor connected from this pin to ground is recommended. When an oscillator is used, keep this pin floating. 25MHz Clock Output. These pins provide general purpose 25MHz clock outputs that are free running after power is stable, and are low jitter (50 ppm), with a 45 ~ 65% duty cycle. This 25Mhz clock could be used for Gigabit 1000Base-TX PHY reference clock input. User Defined Data IO. Used to define a level of detected input signal for system fault event management. The defined level is written to the internal registers. These pin are internally pulled-low. These pins may be used for external trigger signal input, for example, FAN fault, Thermal Fault, Factory Reset, or any other sensor detection.
XI/OSCI
I
110
XO
O
111
G0_25MCKO G1_25MCKO
O
78 125
USR_IO[3:0]
I (Pd)
182 183 184 185
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RTL8326 Datasheet
6.6. Mode Control Pins
Note: The Mode Control pin values are strapped on power on reset. The strapped values may be updated via EEPROM configuration if it exists. They can also be modified by internal register access from the CPU interface.
Symbol MaxPktLen[1:0]/ [P3TXD, P2TXD] Type I (Pd, Pd) Table 8. Mode Control Pins Pin No. Description 13, 9 Max. Valid Packet Length Control. 00: 1536 bytes (Default) 01: 1552 bytes 1x: Reserved 16 Transmit IPG (Inter-Packet Gap) Compensation. Used to compensate the oscillator frequency or incoming packet IPG tolerance. 0: +65 ppm TXIPG compensation (Default) 1: +90 ppm TXIPG compensation 18 Max Pause frame Count for Congestion Control. 0: 128 (Default) 1: Continuous 140 Enable Carrier-Based Back Pressure Mode. Half duplex back pressure flow control algorithm selection. 0: Collision-based back pressure mode 1: Carrier-based back pressure mode (Default) 7, 5 Force Enable Gigabit port at TBI Mode Interface of Port G0 or G1. FrcTBImode[0], for Gigabit port 0 FrcTBImode[1], for Gigabit port 1 0: Enable GMII/MII Mode Interface (Default) 1: Enable TBI Mode Interface. Note: After the Gigabit Port Interface Mode is selected, the port will be auto disabled whenever the interface receive clock is idle for a defined timeout period. Disable Realtek Remote Control Protocol Function. 0: Enable RRCP (Default) 1: Disable RRCP Disable Realtek Echo Function. 0: Enable REcho (Default) 1: Disable REcho Enable 802.1D Specified Reserved Control Frame Filtering. When network control frames are received with the destination MAC address as the group MAC address: (01-80-C2-00-00-03 ~ 01-80-C2-00-00-0F), the switch will drop the frames if the EnCtrlFilter=1. If EnCtrlFilter=0 the frames will be flooded. 0: Disable Filtering 1: Enable Filtering (Default) Enable IGMP Snooping. 0: Disable (Default) 1: Enable
TXIPG_Comp/ P4TXD
I (Pd)
MaxPauseCnt/ P5TXD EnCRSBKPmode/ G1TX_EN
I (Pd) I (Pu)
FrcTBIMode[1:0]/ [P1TXD, P0TXD]
I (Pd)
DisRRCP/ P10TXD DisREcho/ P11TXD EnCtrlFFilter/ P13TXD
I (Pd) I (Pd) I (Pu)
35
37
42
EnIGMPsnooping/ P14TXD
I (Pd)
46
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RTL8326 Datasheet
Symbol EnHomeVLAN/ P15TXD Type I (Pd) Pin No. 51 Description Enable Home-VLAN Configuration. When enabled, the switch will be configured in 24VLAN mode, "Home-VLAN topology". That is, ports 0~23 are all individual VLANs shared with two port members, Gigabit ports 0 & 1. 0: Disable (Default) 1: Enable High Priority Port Setting of Port-based QoS Function. 00: No high priority port (Default) 01: Set port 0 as high priority ports 10: Set ports 0, 1 as high priority ports 11: Set ports 0, 1, 2, 3 as high priority ports Enable 802.1p VLAN Tag-based Priority QoS Function. 0: Disable (Default) 1: Enable Enable TCP/IP TOS/DS (DiffServ) based Priority QoS Function. 0: Disable (Default) 1: Enable High Priority: If TOS/DS[0:5]: (EF) `101110'; (AF) `001010', `010010', `011010', `100010'; (Network Control) `11x000'; Low Priority: If TOS/DS: Other then Codepoint values are applied. Weighted Round Robin Ratio Setting of Priority Queue. The frame service rate of High-pri queue: Low-pri queue is. 00: 4:1 01: 8:1 10: 16:1 (Default) 11: 1:0 (always high priority queue first) Enable Flow Control Ability Auto Turn Off for QoS Enabled. Enable auto turn-off of a port's queue flow control ability for 1~2 seconds whenever the port receives a high priority frame. The flow control ability of the port will be re-enabled when no high priority frames are received at this port during a 1~2 second period. When EnFCAutoOff is disabled, the flow control ability of this port for any packet will be enabled as set. 0: Disabled (Default) 1: Enabled Global Disable Full Duplex 802.3x Pause Flow Control Ability. Globally disables the 802.3x Pause ability flow control of all ports. 0: Enable 802.3x Pause flow control ability (Default) 1: Disable 802.3x Pause flow control ability Global Disable Half Duplex Back Pressure Flow Control Ability. Globally disables the back pressure flow control ability of all ports. 0: Enable back pressure flow control ability (Default) 1: Disable back pressure flow control ability Disable Back Pressure 48 Pass One Algorithm. When the 48 Pass One algorithm is enabled, the switch will pass one incoming packet for every 48 collisions. 0: Enable 48 Pass One algorithm (Default) 1: Disable 48 Pass One algorithm
PortPriSet[1:0]/ [P22TXD, P21TXD]
I (Pd, Pd)
71, 69
En8021pPri/ P17TXD EnDSPri/ P16TXD
I (Pd) I (Pd)
56
54
QWEIGHT[1:0]/ [P20TXD, P19TXD]
I (Pu,Pd )
67, 62
EnFCAutoOff/ P18TXD
I (Pd)
58
DisFDFC/ P23TXD
I (Pd)
73
DisBKP/ G0TX_EN
I (Pd)
93
DisBKP48One/ P6TXD
I (Pd)
20
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Symbol DisBCSFC/ G0TXDS7 Type I (Pd) Pin No. 81 Description Disable Broadcast Packet Strict Flood Control. Set to disable broadcast packet (DA: `FF-FF-FF-FF-FF-FF') strict flood mode and configure to loose flood mode. Strict flood mode will drop all broadcast packets if any one destination port is congested. Loose flood mode allows broadcast packets to be flooded to all non-congested ports. 0: Enable Broadcast Packet Strict Flood (Strict flood mode) (default) 1: Disable Broadcast Packet Strict Flood (Loose flood mode) Disable IP Multicast Packet Strict Flood Control. Set to disable IP Multicast packet (DA: `01-00-5E-XX-XX-XX') strict flood mode and configure to loose flood mode. Strict flood mode will drop all IP Multicast packets if any one destination port is congested. Loose flood mode allows IP Multicast packets to be flooded to all noncongested ports. 0: Enable IP Multicast Packet Strict Flood (Strict flood mode) (default) 1: Disable IP Multicast Packet Strict Flood (Loose flood mode) Broadcast Storm Filtering Control. Disables broadcast storm filtering control. 0: Enable Broadcast storm filtering control 1: Disable Broadcast storm filtering control (Default) Enable Loop Detect function. 0: Disable (Default) 1: Enable Enable Gigabit Port Data Sequence Reverse. When set, reverses the sequence of TXD `[7:0]' to `[0:7]'. RXD[7:0] maintains the original sequence. 0: Disable (Default) 1: Enable To delay 2ns on OCT_PHY_2 RXD 0: Delay 0 ns (Default) 1: Delay 2 ns (Recommended) If EEPROM exists, the EEPROM configuration will override the delay configuration set here. To delay 2ns on OCT_PHY_1 RXD 0: Delay 0 ns (Default) 1: Delay 2 ns (Recommended) If EEPROM exists, the EEPROM configuration will override the delay configuration set here. To delay 2ns on OCT_PHY_0 RXD. 0: Delay 0 ns (Default) 1: Delay 2 ns (Recommend) If EEPROM exists, the EEPROM configuration will override the delay configuration set here. Force TBI G0 Link Up. 0: Normal (Default) 1: Force Link Up Force TBI G1 Link Up. 0: Normal (Default) 1: Force Link Up 28 Track ID: JATR-1076-21 Rev. 2.1
DisIPMCSFC/ G0TXDS6
I (Pd)
82
DisBRDCTRL/ G0TXDS5
I (Pu)
83
EnLoopDet/ P9TXD EnGDSRev/ P7TXD
I (Pd) I (Pd)
31
26
OCT2_RXD_ Delay_2ns/ G1TXDS2
I (Pd)
133
OCT1_RXD_ Delay_2ns/ G1TXDS1
I (Pd)
134
OCT0_RXD_ Delay_2ns/ G1TXDS0
I (Pd)
135
TBI_G0_Force_ Link/ G0TXDS3 TBI_G1_Force_ Link/ G0TXDS4
I (Pd) I (Pd)
87
84
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RTL8326 Datasheet
Symbol EnFastAgeTime/ P12TXD EnAcceptErr/ G0TXDS2 Type I (Pd) I (Pd) Pin No. 40 Description Enable Fast Aging Time. 0: 300 sec Aging Time (Default) 1: 12 sec Aging Time (Fast Aging Time) Enable Accept CRC Error packet. Set to enable acceptance of a CRC error packet with valid packet length (64 byte ~ max packet length). 0: Disable accept CRC error packet (Default) 1: Enable accept CRC error packet
88
6.7. LED Pins
Symbol SLED_DMODE_CK Type I Table 9. LED Pins Pin No Description 162 Serial LED Diagnostic Mode Item Select Control Pulse Input. This is an external signal pulse input signal for diagnostic item selection. The diagnostic LED display item will change whenever there is a signal pulse clock input on this pin. The diagnostic items list and its display sequence is as follows: (1) DisablePort/RxError (active low) On: Port disabled Blinking: Error Packet Received (includes dropped packets) (2) FlowControl/FCActive (active low) On: Flow control ability enabled Blinking: Congestion flow control active (3) TrunkPort/TKFault (active low) On: Trunk Port Blinking: Trunk link fault port (4) HighPriorityPort (active low) On: High priority port (5) LoopDetectPort (active low) On: Loop event detected. (6) BroadcastStormAlarmPort (active low) On: Broadcast Storm detected (7) TX Utilization: TX port bandwidth utilization (active low) (8) RX Utilization: RX port bandwidth utilization (active low) 177 Serial LED Shift Clock/Trunk Port 0 Enabled LED output. In Parallel LED mode, acts as Trunk 0 Enable LED. In Serial LED mode, when Serial LED mode is enabled, periodically active to enable SLED_DATA shift into external shift register. 176 Serial LED Data Output/Trunk Port 1 Enabled LED output. In Serial LED mode, when Serial LED mode is enabled, serial LED data is shifted out when SLED_CLK is active. See 7.31 LED Interfaces, page 51 for detailed information.
SLED_CLK/ LED_EnTrunk[0]
O
SLED_DATA/ LED_EnTrunk[1]
O
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RTL8326 Datasheet
Symbol LED_EnTrunk[7:2] Type O Pin No 170 171 172 173 174 175 Description Trunk Port Enabled LED output. 0 (On): Trunk Enabled 1 (Off): Trunk Disabled. The LED blinks to indicate that there is a trunk member port link down. LED_EnTrunk0: (port 0, 1) LED_EnTrunk1: (port 2, 3) LED_EnTrunk2: (port 4, 5, 6, 7) LED_EnTrunk3: (port 8, 9, 10, 11) LED_EnTrunk4: (port 12, 13, 14, 15) LED_EnTrunk5: (port 16, 17, 18, 19) LED_EnTrunk6: (port 20, 21, 22, 23) LED_EnTrunk7: (port G0, G1) Reserved for testing (VLED). Loop Detect LED output. 0: Loop detected 1: Loop not detected Built-In Self Test (BIST) LED output. 0: BIST FAIL 1: BIST PASS Gigabit Ports 1000Mbps Speed Link/Active LED output. This LED show the state information of the Gigabit Port when it is linked at 1000Mbps. The definition of this LED is different in serial mode and parallel mode: In Serial Mode it is 1000M speed In Parallel Mode it is 1000M Link/ Activity 0: Link Up 1: Link Down Blinking: TX/RX Activity (Blinking is 40 ms ON then 40 ms OFF)
Reserved LED_LoopDet
O O
165 166
LED_BISTFail
O
169
LED_GLink/ACT[1:0]
O
163 164
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RTL8326 Datasheet
6.8. Power/Ground Pins
Symbol AVDD AVSS DVDD Type P G P Table 10. Power/Ground Pins Pin No Description 108 3.3V for Phase-Locked Loop (PLL) Power. 113 109 GND for Phase-Locked Loop (PLL). 112 11, 22, 3.3V for IO digital power. 33, 44, 60, 75, 85, 94, 126, 136, 148, 167, 181, 201 12, 23, GND for IO. 34, 45, 61, 76, 86, 95, 127, 137, 149, 168, 202 3, 50, 106, 156 2, 24,179 3.3V for internal 3.3V to 1.8V regulator power input. Note: Pins 3, 50, 106, 156) map to RVDD0, RVDD1, RVDD2, RVDD3. 1.8V for Core power. Generated by internal regulator. Only an external 10uF CAP and bypass CAP are required. Note: DO NOT supply 1.8V power to these pins. 1.8V for Core power. Generated by internal regulator. Only an external 10uF CAP and bypass CAP are required. Note: DO NOT supply 1.8V power to these pins. 1.8V for Core power. Generated by internal regulator. Only an external 10uF CAP and by pass CAP are required. Note: DO NOT supply 1.8V power to these pins. 1.8V for Core power. Generated by internal regulator. Only an external 10uF CAP and by pass CAP are required. Note: DO NOT supply 1.8V power to these pins. GND for Core power.
DGND
G
RVDD
P
VDD0
P
VDD1
P
49, 64
VDD2
P
91, 105
VDD3
P
138, 157
GND
G
4, 25, 48, 65, 92, 107, 139, 158, 180,
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6.9. Test Pins
Symbol ExtSysCLKI EnExtSysCLK Ext125CLKI EnExt125CLK EnExt18VPwr EnTESTMODE TEST_PIN [17:0] Type I I (Pd) I I (Pd) I (Pd) I (Pd) IO Table 11. Test Pins Pin No Description 115 Test pin. Normally kept floating. 114 Test pin. Normally kept floating. 117 Test pin. Normally kept floating. 116 Test pin. Normally kept floating. 1 Test pin. Normally kept floating. 186 Test pin. Normally kept floating. 187, 188, Test Pins. 189, 190, Normally kept floating. 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 203, 204, 205, 206
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RTL8326 Datasheet
7.
Functional Description
7.1. Reset
7.1.1. Hardware Reset
In a power-on reset, an internal power on reset pulse (44ms) will be generated and the RTL8326 will start the reset initialization procedures. These are: 1. Determine various default settings via the hardware strap pins at the end of the RST# signal 2. Auto load the configuration from EEPROM if EEPROM is detected (approx. 10ms) 3. Complete the embedded SSRAM BIST process (approx. 24 ms) 4. Initialize the packet buffer descriptor allocation 5. Initialize the internal registers and prepare them to be accessed by the serial CPU interface 6. Start MDC/MDIO configuration and polling Note 1: To guarantee register access is valid and correct, the RTL8326 registers should not be accessed before the reset initialization process is finished. Note 2: The connected PHY should have completed the reset process before the RTL8326 starts the MDC/MDIO configuration and polling process.
7.1.2.
Software Reset
The software reset command resets the system control circuit and restarts auto-negotiation. It keeps the user configured settings. Hardware pin strapping, EEPROM auto load, and SSRAM BIST are NOT done when using the software reset command.
7.2. MAC to PHY Interface
The MAC to PHY interface supports SMII for 10/100M ports, and GMII/MII/TBI for Gigabit ports. Two 25Mhz clock outputs for external Gigabit PHY save BOM costs.
7.3. Fast Ethernet Port (SMII Interface)
Ports 0~23 are 10/100M Fast Ethernet ports supporting a Serial Media Independent Interface (SMII). The RTL8326 provides three SMII synchronous 125Mhz clock outputs for three octal PHYs. The SMII RXD IO delay control and Reference clock delay control are supported by configuring register 0x0002~ 0x0003. This function allows SMII timing fine-tuning for different PCB layout traces. The default values are optimized for SMII interface timing.
7.4. Gigabit Ethernet Ports (GMII/TBI/MII)
The Gigabit Ethernet ports may be configured as GMII (Gigabit Media Independent Interface), TBI (TenBit Interface), or MII (Media Independent Interface) mode to support 1000Base-T, 1000Base-X, and
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RTL8326 Datasheet
10Base-T/100Base-TX modes. These interface modes are enabled by hardware configuration pins FrcTBIMode[1:0]: GMII TXD/RXD IO delay control is also supported on register 0x0002~0x0003. When configured as a GMII or TBI interface, only full-duplex operation is supported. When configured as an MII interface, both full and half-duplex operations are supported.
7.5. GMII/MII/TBI Signal Mapping
GMII/MII/TBI support is implemented via the same hardware pins. The signal mapping is shown in the following table:
GMII GTX_CLK(125Mhz) GTXD0 GTXD1 GTXD2 GTXD3 GTXD4 GTXD5 GTXD6 GTXD7 GTX_EN GRX_CLK(125Mhz) GRXD0 GRXD1 GRXD2 GRXD3 GRXD4 GRXD5 GRXD6 GRXD7 GRX_DV Table 12. GMII/MII/TBI Signal Mapping MII TBI G_TXCLK(125Mhz) GTXD0 GTXDS0 GTXD1 GTXDS1 GTXD2 GTXDS2 GTXD3 GTXDS3 GTXDS4 GTXDS5 GTXDS6 GTXDS7 GTX_EN GTXDS8 GTXDS9 GRXC(2.5/25Mhz) GRSCK0(62.5Mhz) GTXC(2.5/25Mhz) GRSCK1(62.5Mhz) GRXD0 GRXDS0 GRXD1 GRXDS1 GRXD2 GRXDS2 GRXD3 GRXDS3 GRXDS4 GRXDS5 GRXDS6 GRXDS7 GRX_DV GRXDS8 GRXDS9 GCRS GCOL IO O O O O O O O O O O O I I I I I I I I I I I I I I
In TBI interface mode, the RTL8326 implements a built-in PCS (Physical Coding Sublayer) for SERDES transceiver applications. The PCS function implemented by the RTL8326 comprises: * * * * * PCS Transmit process PCS Receive process 8-bit to 10-bit Encoding and 10-bit to 8-bit Decoding Synchronization process Auto-negotiation process for 1000BASE-X.
Note: Half-duplex is not supported by the RTL8326's Gigabit PCS).
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RTL8326 Datasheet
7.6. MAC Address Table Search and Learning
The RTL8326 MAC address lookup table consists of an 8K-entry hash table and 64-entry CAM. The RTL8326 uses the last 13 bits of the MAC address to index the 8K-entry lookup table for address searching and learning. If the mapped location in the 8K entries is occupied, then the RTL8326 will compare the destination MAC address with the contents of the CAM for address searching and store the source MAC address to the CAM for address learning. The 128-entry CAM helps avoid address hash collisions and improves switch performance.
7.7. MAC Table Aging Function
In a dynamic network topology, address aging allows the contents of the address table to always be the most recent and correct. A learned source address entry will be cleared (aged out) if it is not updated by the address learning process within a set aging time period. The default aging timer of the MAC address lookup table is between 200 ~ 300 seconds.
7.8. Illegal Frame Filtering
Illegal frames such as CRC error packets, runt packets (length < 64 bytes) and oversize packets (length > maximum length) will be discarded. The max. packet length may be 1536 or 1552 bytes and is controlled by register 0x0001.
7.9. 802.1D Reserved Group Addresses Filtering Control
The RTL8326 supports the ability to drop 802.1D specified reserved group MAC addresses: 01-80-C200-00-03 to 01-80-C2-00-00-0F. The RTL8326 default setting enables dropping of these reserved group MAC address control frames. Frames with group MAC address 01-80-C2-00-00-01 (802.3x Pause), 0180-c2-00-00-02 (802.3ad LACP) will always be filtered.
7.10. Backoff Algorithm
The RTL8326 implements the truncated exponential backoff algorithm compliant with the IEEE 802.3 standard. The collision counter is restarted after 16 consecutive collisions.
7.11. Inter-Packet Gap
The Inter-Packet Gap is 9.6s for 10Mbps Ethernet, 960ns for 100Mbps fast Ethernet, and 96ns for Gigabit Ethernet. The RTL8326 supports Transmit Inter-Packet Gap compensation for the frequency shift tolerance of the on-board oscillator, which is controlled by register 0x0001.
7.12. Buffer Management
An embedded 2.5Mbit SSRAM is built-in as a packet storage buffer. To efficiently utilize the packet buffer, the RTL8326 divides the SSRAM into 2.5k 128-byte page-based buffers that are linked by a descriptor link list. For an Ethernet packet, a minimum of one, and maximum of 12 pages can be used. The system supports 24 10/100M ports plus 2 Gigabit ports non-blocking wire speed switching.
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RTL8326 Datasheet
7.13. Flow Control
The RTL8326 supports IEEE 802.3x full-duplex flow control, and half-duplex back pressure congestion control.
7.13.1. 802.3x Pause Flow Control
IEEE 802.3x flow control is auto-negotiated between the remote device and the RTL8326 by writing the flow control ability, via MDIO, to an external connected PHY. If a good PAUSE frame is received from any PAUSE flow control enabled port with DA=0180C2000001, the corresponding port of the RTL8326 will stop its packet transmission until a PAUSE timer timeout or another PAUSE frame with zero PAUSE time is received. The maximum transmitted Pause frame count during a congestion event is controllable. (1) limited to a 128 count (2) unlimited count. The limited count is used to avoid unexpectedly long pause time locks for some network topology traffic. This is controlled by register 0x0001.
7.13.2. Half Duplex Back Pressure Flow Control
The RTL8326 supports two back pressure flow control schemes to force incoming packet backoff when the switch destination port is congested. The back pressure mode is controlled by `EnCRSBKPMode' at register 0x0001. A hardware control pin is supported. Collision-based back pressure: Uses a 4-byte jam pattern to force collisions with each incoming packet to force the link partner to back off transmissions according to CSMA/CD until the destination port congestion event is cleared. The RTL8326 uses a special half-duplex back pressure design; after 48 forced collisions it unconditionally receives and forwards one packet successfully. This prevents the connected repeater from being partitioned due to excessive collisions. Carrier sense-based back pressure: When a congested event is asserted, the RTL8326 continuously sends 4k jam packets with a minimum Inter-Packet Gap to prevent the link partner from transmitting more packets.
7.14. Broadcast Storm Filtering Control
The RTL8326 supports broadcast storm filtering control via hardware pin `DisBRDCTRL' or register 0x0607. This function enables each port to drop broadcast packets (Destination MAC ID is `ff ff ff ff ff ff') after a continuous received broadcast packets counter count of 64. The counter is reset to 0 every 800ms or when receiving non-broadcast packets (Destination MAC ID is not `ff ff ff ff ff ff').
7.15. Head-Of-Line Blocking Prevention
The RTL8326 incorporates a simple mechanism to prevent Head-Of-Line blocking problems when flow control is disabled. When the flow control function is disabled, the RTL8326 first checks the destination address of an incoming packet. If the destination port is congested, then the RTL8316 discards this packet to avoid blocking following packets destined for a non-congested port.
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RTL8326 Datasheet
7.16. Port Trunking and Fault Recovery Support
Port Trunking is the ability to aggregate several 10/100Mbps ports or several gigabit ports into a single logical link. There are 8 trunk groups supported by the RTL8326. They are identified as: Trunk 0: (Port 0, 1) Trunk 1: (Port 2, 3) Trunk 2: (Port 4, 5, 6, 7) Trunk 3: (Port 8, 9, 10, 11) Trunk 4: (Port 12, 13, 14, 15) Trunk 5: (Port 16, 17, 18, 19) Trunk 6: (Port 20, 21, 22, 23) Trunk 7: (Port G0, G1) They are individually enabled by Register 0x0307 EnTrunk[7:0] during hardware reset. Each trunk supports a trunking port status LED. The LED will be active low when the trunking function is enabled. The RTL8326 trunking port always sends packets over the same link path in the trunk with a given source and destination MAC address to prevent frames from getting out of order, but the reverse path may follow a different link.
7.16.1. Load Balancing
The load balancing scheme between links in a trunk group is determined by an Index[2:0] value that is calculated by a DA and SA hash algorithm. Mapping algorithm. Given a number between 8 values of Index[2:0], If link up port is 4. Index value {(7, 6), (5, 4), (3, 2), (1, 0)} maps to LinkUpPort[3:0] If link up port is 3. Index value {(7, 6, 5), (4, 3, 2), (1, 0)} maps to LinkUpPort[2:0] If link up port is 2. Index value {(7, 6, 5, 4), (3, 2, 1, 0)} maps to LinkUpPort[1:0] If link up port is 1. Index value {(7, 6, 5, 4, 3, 2, 1, 0)} maps to LinkUpPort[0]
7.16.2. Trunk Fault Auto Recovery
If a physical port of a trunk group is link down, then the TrunkLED will blink to warn of a link-down fault event. The Fault flag will be reported on register 0x0102 (System Fault Indication Register). The RTL8326 will auto-start the Auto Fault Recovery scheme to distribute the trunk load to the remaining link up ports.
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7.17. IGMP Snooping Support
The RTL8326 supports ASIC-based IGMP (Internet Group Management Protocol) snooping. This can be enabled via register 0x0308 and no other external CPU handling is required. It supports the ability to parse the IGMP control protocol packets and IP multicast data packets and learn the multicast router port and group address member ports into the multicast address table. The RTL8326 differentiates between IGMP control protocol packets according to the message type: * * Router protocol packets (IGMP query packets and multicast routing protocol packets) are broadcast to all ports. Group member protocol packets (IGMP v1, v2 Report and Leave packets) are sent directly to multicast router ports.
IP multicast data packets involve multicast group table lookup and forwarding operations. If the table lookup returns a hit, the data packet is forwarded to all member ports and router ports. If the multicast address is not stored in the address table (i.e. lookup miss), the packet is broadcast to all ports of the broadcast domain. The multicast table is combined with a L2 MAC table with a maximum of 8k entries. For a given multicast entry, the valid port member bit will auto age out after about 5 min if the port does not receive a corresponding group address IGMP report packet.
7.18. VLAN Function
The RTL8326 supports a VLAN function to segregate the switch into 32 VLANs. Each VLAN is a broadcast domain and each VLAN may be flexibly configured from 0 to 26 port members. Both portbased and tag-based VLAN functions are supported. The PVID, Tagging Control, and Ingress/Egress rules are manually configured on the VLAN Table at registers 0x030B~0x037C. The VLAN table format is shown as follows:
VLAN Entry Index 0 1 2 : 31 Table 13. VLAN Table Format VID (12-Bit) Port Member Set (26-bit Bitmap)
`VID' defines the 802.1Q VLAN ID. The value of `VID' may NOT be `0x000' or `0xfff'. `Port Member Set' defines the VLAN group members via a 26-bit bitmap.
Table 14. Port VLAN ID (PVID) Assignment Table Port No. "PVID Index for 802.1Q VLAN" or "VLAN Index for Port-based VLAN" (5-bit addressing to 32 VLAN entries) 0 1 2 : 25 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller 38 Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
The per-port default Port VLAN Identifier (PVID) is defined at PVID register (0x030C~0x0318) which is a VLAN table entry index mapped to a 12-bit VID. Each port should be assigned a unique PVID. The VID of each VLAN Table entry should be different. Overlapping port groups are allowed. This feature makes it easy to allow a server port to be shared between different VLAN groups without routing through an external router device. A VLAN is used to divide the broadcast domain to cut broadcast scope. The VLAN Frame Forwarding Rules are defined as follows: * * A received broadcast/multicast frame will be flood forwarded to VLAN member ports only (`Port Member Set' in the VLAN table) of the VLAN except the source port. A received unicast frame will be forwarded to its destination port only if the destination port is in the same VLAN as the source port. If the destination port belongs to a different VLAN, the frame will be discarded unless Leaky VLAN control is enabled. All VLAN groups share the same layer-2 learned MAC address table (Shared Learning).
*
7.18.1. Port-based VLAN
By setting the 0x030B register to disable the En8021Qaware control bit, port-based VLAN is enabled and 802.1Q VLAN tagging is ignored. All other VLAN table configurations are the same as tag-based VLAN functions. The VLAN classification of an incoming packet on a port-based VLAN is defined by the port PVID. The RTL8326 uses the Port VLAN Identifier (PVID) to search the VLAN table for the VLAN member.
7.18.2. 802.1Q Tag-based VLAN
By setting the 0x030B register to enable the En8021Qaware control bit, 802.1Q tag-based VLAN is enabled. VLAN classification is the first step before VLAN table lookup. The method of assigning a unique VID value to a received packet is as follows: 1. For a VLAN-tagged packet. If the tagged 12-bit VID != 0, then the tagged VID value is used. If the tagged VID = 0 (Null VID, priority tag), then the port's PVID value is used. 2. For a non-VLAN-tagged packet. The port's 12-bit PVID value is used. After the unique 12-bit VID is assigned, the RTL8326 checks the VLAN table ingress/egress rule, and then forwards the packet to valid destination ports.
7.18.3. Ingress/Egress Filtering Control Parameters
Two VLAN filtering rule control parameters are provided on register 0x030B: * * Acceptable frame type control: Admits all frames or admits only VLAN-tagged frames. Ingress filtering control: Enables filtering of frames received from a port that is not in this port's VLAN group.
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7.18.4. Leaky VLAN
The Leaky VLAN feature enables specific frames to be forwarded between different VLANs. For example, if the VLAN table entry is: VLAN 1: Port members = { Port 1, 2, 3 } VLAN 2: Port members = { Port 4, 5, 6} Normally, broadcast/multicast, and unicast packets not allowed to be switched between these two VLANs. Port 1 broadcast packets will only flood to Port 2 and 3. A Port 1 unicast packet is not allowed to be forwarded to a member of VLAN 2. If the Leaky VLAN function is enabled, three types of packets may be forwarded to destination ports outside the current VLAN. 1. Unicast Packet: May be forwarded to a destination port (L2 table lookup hit) on a different VLAN. 2. ARP Broadcast Packet: May be broadcast to all ports on a switch. 3. IP Multicast Packet: May be flooded to all the multicast address group member set, ignoring the VLAN member set domain limitation. These types of leaky control are used when: * * a switch is divided into multiple VLANs and host to host communication is required between the different VLANs without using a router. you want to improve router performance.
7.18.5. Insert/Remove VLAN Priority Tag
The RTL8326 supports Output Priority tagging control via register set 0x0319~0x031C. There are four types of VLAN tagging: 1. Remove the VLAN tag from all tagged packets. 2. Insert a priority tag into untagged high-priority packets (Set priority field: 7, VID field: 0 for high priority packet). 3. Insert a priority tag into all untagged packets. (Set priority field: 7, VID field: 0 for high priority packet; Set priority field: 0, VID field: 0 for low priority packet.) 4. Don't touch (No modification made to the packet). Note: This function may be enabled whether the VLAN function is enabled or not.
7.19. QoS Function
The RTL8326 can recognize QoS priority information in an incoming packet and send the packet to different priority queues for different service priority. The RTL8326 identifies the packet's priority based on three types of QoS priority information: 1. Port-based priority 2. 802.1p/Q VLAN tag 3. TCP/IP TOS/DiffServ (DS) priority field
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RTL8326 Datasheet
These three types of QoS can be configured via hardware pins, EEPROM, or Registers 0x0400 and 0x0401. The RTL8326 supports two priority level queues. The queue service rate is based on the Weighted Round Robin algorithm. The packet-based service weight ratio of high-priority and low-priority queuing can be set as 4:1, 8:1, 16:1 or `Always high priority first'.
7.19.1. Port-Based Priority
When port-based priority is applied, any packet received from a high priority port will be treated as a high priority packet.
7.19.2. 802.1p/Q Based Priority
When 802.1p tag priority is applied, the RTL8326 recognizes 802.1Q VLAN tagged packets and extracts the 3-bit User Priority information from the VLAN tag. The RTL8326 sets the User Priority threshold to 3. VLAN tagged packets with User Priority values 4~7 are treated as high priority packets, and other User Priority values (0~3) as low priority packets (follows the IEEE 802.1p standard).
7.19.3. Differentiated Service Based Priority
When TCP/IP's TOS/DiffServ (DS) based priority is applied, the RTL8326 recognizes TCP/IP Differentiated Services Codepoint (DSCP) priority information from the DS-field defined in RFC2474. The DS field byte for IPv4 is the Type-of-Service (TOS) octet, and for IPv6, it is the Traffic-Class octet. Recommended DiffServ Codepoints are defined in RFC2597 for classifying traffic into different service classes. The RTL8326 extracts the codepoint value of the DS field from IPv4 and IPv6 packets and identifies the priority of the incoming IP packet following the definitions listed below: High Priority. DS-field = 101110 (EF, Expected Forwarding) 001010; 010010; 011010; 100010 (AF, Assured Forwarding) 11x000 (Network Control) Low Priority. DS-field = Other values VLAN tagged packet formats are shown below:
6 bytes DA 6 bytes SA 2 bytes 81-00 3 bits User Priority (0~3: Low-pri; 4~7: High-pri) 5 bits ---Data 4 bytes CRC
Figure 4. 802.1Q VLAN Tag Frame Format 6 bytes DA 6 bytes SA 4 bytes 802.1Q Tag (Optional) 2 bytes 08-00 4 bits Version IPv4: 0100 4 bits IHL 6 bits TOS[0:5]: DS-field 2 bits ---4 bytes CRC
Data
Figure 5. IPv4 Frame Format 6 bytes DA 6 bytes SA 4 bytes 802.1Q Tag (Optional) 2 bytes 08-00 4 bits 6 bits Version Traffic Class [0:5] IPv6: 0110 =DS-field 2bits ---4 bytes CRC
Data
Figure 6. IPv6 Frame Format
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7.19.4. Flow Control Auto Turn Off
The RTL8326 can automatically turn off 802.3x flow control and back pressure flow control for 1~2 seconds whenever the port receives a high priority packet. Flow control is re-enabled when no priority packet are received for 1~2 seconds. This auto-turn off function is enabled via hardware pin EnFCAutoOff or Register 0x0400.
7.20. Ingress and Egress Bandwidth Control
The RTL8326 supports bandwidth control on all ports. Each port's bandwidth is configurable on both ingress and egress traffic independently. Port bandwidth may be configured as: 128kbps, 256kbps, 512kbps, 1Mbps, 2Mbps, 4Mbps, or 8Mbps. When the ingress or egress traffic bandwidth exceeds the configured threshold, flow control is triggered to limit the throughput. The control description is shown in register 0x020A ~0x0216, page 73.
7.21. Simple MIB Counter Support
Three 32-bit MIB counters (Counter 1, Counter 2, and Counter 3) are implemented on each port for basic traffic management and diagnostic purposes. The MIB object of each counter is configurable. The MIB object selection on each counter is shown in Table 15. A detailed description is given in 9.8 MIB Counter Registers, page 12.
Table 15. MIB Object Selection MIB Object Counter 1 Counter 2 RX Packet Count V RX Byte Count V TX Packet Count TX Byte Count Drop Packet Count Drop Byte Count CRC Error Packet Count Collision Count V V V V V V Counter 3 V V V V
7.22. RRCP(R) Realtek Remote Control Protocol
The RRCP is a Realtek proprietary simple and easy device management program that is implemented for in-band remote control purposes. The protocol is hardware ASIC based and does not require an external CPU. It allows the system administrator to get/set the switch configuration, to read the statistic counters, and to find RRCP aware devices. The Remote Management Tool (RMT) software package is bundled with the RTL8326. The RMT is a Windows-based tool developed to enhance the functionality of Realtek's dumb layer 2 switches via software. The RMT gives network administrators the ability to remotely configure and monitor dumb layer 2 switches as though they were intelligent switches.
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7x Ethernet C 7 8 9 1011 12 A 12 34 56 1x 2x 3x 4x 5x 6x 1x 2x 3x 4x 5x 6x 8x 9x 10x 11x 12x 7x 8x 9x 10x 11x 12x A B
Realtek RRCP Protocol Get, ) commands ( Set, Hello
user
IaY
Figure 7. Realtek Remote Control Protocol
7.22.1. RRCP Capabilities
The RRCP is limited to the same network domain. The RRCP supports the following: 1. Network Topology Discovery 2. Get/Set Configuration value of Register 3. Security Management by an Authentication Key and management port setting Operation commands are: Management Operation
(1) register Get (2) register Set (3) Hello
(1) register Get Reply (2) Hello Reply The Hello Reply packet reports the switch's link vector information back to the manager (Downlink MAC, Downlink Port), (Uplink MAC, Uplink Port). The link vector information enables discovery of the network topology.
Switch Operation
7.22.2. Management Security Scheme
Two RRCP security schemes are implemented: RRCP Management Authorized Port Control An authorized port can be configured via registers 0x0201~0x0202. Only RRCP packets originating from an authorized port will be processed and responded to. Other RRCP with DA=switch's MAC address will be dropped.
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Protocol Authentication Key control Each RRCP packet must contain the Authentication Key defined in the register 0x0209. After powering on, the Authentication Key is reset to the default value (0x2379). It can be updated through a valid RRCP Set command or through a Serial CPU interface.
7.22.3. RRCP(R) Protocol Packet Format
Hello/Get/Set/Get_Reply Packet Format
0 DA SA RealtekEtherType (2) Authentication Key (2) Protocol (1) r OP Code (7bit) Register Address (2) Register Data (4) Reserved (4) Reserved (4) Pad 00 : : CRC (4) Figure 8. Hello/Get/Set/Get_Reply Packet Format 8 DA (6) SA (6) 16 24 32
Field DA
SA RealtekEtherType Protocol
OP Code
r
Table 16. Hello/Get/Set/Get_Reply Packet Format Description Length Description Value -6B Destination MAC Address. -For a Get, Set Packet, this is the unicast address of a switch. -For a Get_Reply Packet, this is the unicast address of the management station. -For a Hello Packet, this can be the unicast address of a switch or a broadcast address to all RRCP aware switches. Note: If the Authentication Key register has been updated after power on, the switch will only respond to a unicast Hello Packet. 6B Source MAC address. -2B Identifies the packet as a Realtek Remote Control 0x8899 packet. The EtherType value=0x8899. 1B Realtek Proprietary protocol type definition. 01h 01: Realtek Remote Control Protocol Others: Reserved 7bit Operation Code (7bit). -Code definition. 00: Hello packet 01: Get configuration 02: Set configuration 1 bit Reply flag. Station to switch: 0 On receiving a control packet reply from the Switch to station: 1 switch to the management station, this flag will be set to 1. Otherwise, this bit should be 0. 44 Track ID: JATR-1076-21 Rev. 2.1
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Field Authentication Key Length 2B Description Authentication Key. Used for security of the management operation. The default Authentication key value is 0x2379. The Key value can be modified by the administrator via a remote control packet. A received control packet with a valid Destination MAC address but with an unmatched authentication key will be dropped with no reply. If the DA is a broadcast address or is the address of another switch, it still will be relayed. Register address of the configuration. Register data of the configuration. Value Default: 0x2379
Register Address Register Data
2B 2B
---
Hello_Reply Packet Format
0 DA 8 DA (6) SA (6) SA (=Downlink MAC) RealtekEtherType (2) Protocol (1) r OP Code (7bit) Authentication Key (2) Downlink Port (1) Uplink Port (1) Uplink MAC (6) Uplink MAC Chip ID (2) Vender ID (4) Pad 00 : : CRC (4) Figure 9. Hello_Reply Packet Format 16 24 32
Field Downlink Port
Uplink Port
Uplink MAC
Chip ID
Table 17. Hello_Reply Packet Format Description Length Description 1B Downlink Port number of the link vector. Indicates the port number on the Hello Reply switch that is connected to the Uplink switch. This is set by the Hello reply switch. 1B Uplink Port number of the link vector. Indicates the port number of the Uplink switch that is connected to the Hello reply switch. This is set by the Uplink switch. 6B The MAC address of the Uplink switch. The default value is 000000000000h and is updated by the Uplink switch. When a switch receives a Hello_Reply frame with zero UplinkMAC, then it will enter the SA MAC address here. 2B Realtek Chip ID. This is set by the Hello_Reply switch. Each Realtek switch controller that is aware of the RRCP has a unique Chip ID (see 10.4.7 0x0206H: Chip Model ID, page 72). 45
Value --
Default=00h Updated by the Uplink_MAC switch Default: 0
EEPROM
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Field Vender ID Length 4B Description Vender ID. This is set by the Hello_Reply switch. The 4-byte vender ID is reserved for the system vender to configure its company name or the device model ID. Value EEPROM
7.23. Network Loop Connection Fault Detection
The RTL8326 periodically transmits a Realtek-EtherType (=0x8899) protocol frame to detect network loop faults. * * * Normal transmission time interval is five minutes If a port detects a loop, the loop event flag will be set (register 0x0101) and the transmission time interval will change to one second to speed up the new topology change detection. The loop event flag will be cleared and the transmission time interval will return to five minutes if the port does not receive a self-loop detect packet for 3 seconds.
Loop Detect Packet Format The Loop Detect Packet Format is shown below:
8 16 24 32 DA (6) [=0xffffffffffff] DA SA (6)[=Switch MAC] SA RealtekEtherType (2) [=0x8899] Protocol (1) [=03] Pad 0000 Pad 00000000 : : CRC (4) Figure 10. Loop Detect Packet Format 0
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7.24. Realtek Echo Protocol
The Realtek Echo Protocol (REP) supports the Layer 2 Echo test. It is easy for a host to do network connection diagnostics through a simple test packet, with or without other hosts on the network. No IP assignment is required. When the RTL8326 receives a REP packet, it replies by sending the original REP frame to the source MAC address with the DA and SA exchanged. Realtek Echo Protocol Frame The REP frame format is shown below:
8 16 24 32 DA (6) [=0xffffffffffff] DA SA (6)[=Switch MAC] SA RealtekEtherType (2) [=0x8899] Protocol (1) [=02] Pad 0000 Pad 00000000 : : CRC (4) Figure 11. Realtek Echo Protocol Frame 0
7.25. Port Security Control
The RTL8326 supports a scheme for port security control by per-port disabling of MAC address autolearning (register 0x0301~0x0302) and enabling of dropping packets with an unknown destination MAC address (register 0x0300). This feature requires that the MAC table aging process is disabled (to keep the known MAC address table static). If port security control is enabled, all incoming packets with unknown destination MAC addresses will be dropped. A detected unknown source MAC address will be captured on register 0x0303~0x0306. The RTL8326 also supports a fast aging time setting (12 seconds) to quickly refresh the MAC address table (register 0x0300). A detailed description is given in Table 56, page 75, register 0x0300 ~ 0x0306.
7.26. Disable Port
A port can be disabled via the Port Disable Control Register (register 0x0608~0x0609). When a port is disabled, the port will cease all packet transmission and reception except for Realtek Remote Control Protocol (RRCP) packets. The physical link status is not changed.
7.27. Port Properties Configuration
The RTL8326 supports a flexible method to configure port properties via the PHY MII registers. Configurable properties include Media Speed (10M/100M/1000M), Duplex Mode, and 802.3x PAUSE flow control. The properties of each can be configured by auto-negotiation or force mode (disable auto negotiation). The port link state will be reported in the port Link Status registers. The configuration description is shown in registers 0x060A ~ 0x0625.
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Gigabit Port Pause Ability configuration is as follows:
Table 18. Gigabit Port Pause Local Device Setup (DUT) Link Partner Setup Target Resolution (Testing Device) PAUSE ASM_DIR PAUSE ASM_DIR Local Resolution Link Partner (1000Base-X: (1000Base-X: (1000Base-X: (1000Base-X: Resolution (DUT) Reg4.7) or Reg4.8) or Reg5.7) or Reg5.8) or (Testing Device) (1000Base-T: (1000Base-T: (1000Base-T: (1000Base-T: Reg4.10) Reg4.11) Reg5.10) Reg5.11) 1 1 Enable Enable PAUSE TX/RX PAUSE TX/RX 1 1 0 1 Enable PAUSE RX Enable PAUSE TX Disable PAUSE Enable PAUSE TX Enable PAUSE RX Disable PAUSE
0
1
1
1
Others
Others
The following shows how to configure the Pause and Asymmetric Pause ability on port property registers (0x060A~0x0616) to get an expected negotiation result.
PAUSE 0 0 1 1 Table 19. Configuring Pause and Asymmetric Pause Asymmetric PAUSE Expected PAUSE Result 0 Disable 1 Asymmetric to Link Partner 0 Symmetric 1 Asymmetric to Link Local or Symmetric
7.28. Serial CPU Interface
The RTL8326 supports a serial CPU interface (Slave mode) that shares the same hardware pin (SCK, SDA) as the EEPROM interface (Master mode). The EEPROM and Serial interface can coexist by assigning a different device ID. Define EEPROM device ID=1010-000, RTL8326 device ID=1010-100. The interface is compatible with EEPROM 24LC024.
SCLK RTL8326
SDA
EEPROM
CPU(8051)
Figure 12. Serial CPU Interface
The serial CPU interface is enabled after the EEPROM download has finished. When operating in serial CPU mode the SCK is an input pin. The SDA is an IO pin with internal pull high.
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7.28.1. Serial-CPU Access Format
In Serial CPU mode, 16-bit and 32-bit data access are both supported by the RTL8326. The Serial Read Write access format is as follows. * * * 16-bit Address (MSB first) 16/32-bit data Burst Read (Low byte (Byte0) first; MSB first) 16/32-bit data Burst Write (Low byte (Byte0) first; MSB first)
Note: Each burst is one byte. Start and Stop Definition (START; STOP) A high-to-low transition of SDA with SCLK high is a START condition and it must precede any other command. A LOW to HIGH transition of the SDA line while the clock (SCLK) is HIGH determines a STOP condition. All operations must end with a STOP.
Figure 13. Start and Stop Definition
Output Acknowledge (ACK) When addressed, each receiving device is obliged to generate an acknowledgment after reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledgement bit.
Figure 14. Output Acknowledge (ACK)
Data Valid The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.
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Serial CPU 16-Bit Read/Write Format
Bit Width Operation 1 Start Bit 4 Control code 3 1 1 Chip R/~W Ack Select 8 Reg. Addr. [7:0] (MSB first) 1 Ack 8 Reg. Addr. [15:8] (MSB first) Write Data Write Data 1 Ack 8 Reg. Data. [7:0] (MSB first) Read Data Write Data 1 Ack 8 Reg. Data [15:8] (MSB first) Read Data Write Data 1 Ack 8 Stop Bit
16-bit Read
Start
1010
100
1
0 Write (*A) Data 0 Write (*A) Data
0 (*A) 0 (*A)
0 (*A) 0 (*A)
0 (*B) 0 (*A)
1 Stop (*B) 1 Stop (*A)
16-bit Write Start
1010
100
0
Figure 15. Serial CPU 16-Bit Read/Write Format
Note: *A = ACK by RTL8326. *B = ACK by CPU
Serial CPU 32-Bit Read/Write Format
Bit Width 1 4 3 11 8 1 8 1 8 1 8 1 8 1 8 1 8 Operation Start Control Chip R/ Ack Reg. Ack Reg. Ack Reg. Ack Reg. Ack Reg. Ack Reg. Ack Stop Addr. Data. Data. Data. Data Bit Bit code Select ~W Addr. [15:8] [7:0] [7:0] [7:0] [15:8] [7:0] (MSB (MSB (MSB (MSB (MSB (MSB first) first) first) first) first) first) 32-bit Read 32-bit Write Start 1010 Start 1010 100 100 1 0 0 0 Write Write 0 0 Write Write 0 0 Read Write 0 0 Read Write 0 0 Read Write 0 0 Read Write 1 1 Stop Stop
(*A) Data (*A) Data (*A) Data (*B) Data (*B) Data (*B) Data (*B)
(*A) Data (*A) Data (*A) Data (*A) Data (*A) Data (*A) Data (*A)
Figure 16. Serial CPU 32-Bit Read/Write Format
Note: *A = ACK by RTL8326. *B = ACK by CPU
7.29. PHY Serial Management Interface
The RTL8326 supports PHY management through the serial MDIO and MDC signal (SMI) to start the auto-negotiation process. After a power-on reset, the RTL8326 writes its abilities to the advertisement registers 0, 4, and 9 of the connected PHY and commands the PHY to restart the auto negotiation process. The PHY device address setting is defined as: Address 2, 3 for port G0, G1 Address 8~31 for Fast Ethernet ports 0~23 After restarting auto-negotiation, the RTL8326 will continuously read the link status and abilities of local and link partners to determine the link state. Port properties (speed, duplex, 802.3x flow control) can be configured via auto-negotiation or force mode. The configuration is described in register 0x060A ~ 0x0616. The final link status is reported in register 0x0619~0x0625.
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7.29.1. SMI (MDC, MDIO) Interface
SMI (MDC, MDIO) Management Packet Format
Table 20. SMI (MDC, MDIO) Management Packet Format Management Frame Fields PRE ST OP PHYAD REGAD TA DATA 1...1 01 10 AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD 1...1 01 01 AAAAA RRRRR 10 DDDDDDDDDDDDDDDD
Read Write
IDLE Z Z
7.29.2. PHY Register Indirect Access
The RTL8326 supports the ability to randomly access PHY registers through a set of control registers at 0x0500~0x0502. Users need to define the PHY address ID, PHY Register ID, Data content of the write command, and operating command type (Read or Write) on the above registers. Then the RTL8326 will auto process the PHY Read/Write access through the MDC/MDIO interface. Read PHY Register Procedure Configure PHY Access Control Register (0x0500) Read the result on PHY Access Read Data Register (0x0502) Write PHY Register Procedure Write the PHY Access Write Data Register (0x0501) Configure the PHY Access Control Register (0x0500) PHY Address ID Definition The PHY address ID corresponds to the port location. The PHY address ID of Ports 0~23 are 0x08, 0x09, 0x0A, ...., 0x1F. The PHY ID of ports 24 & 25 (Gigabit ports G0, G1) are 0x02, 0x03.
7.30. General Purpose I/O Interface
A 4-bit user defined I/O interface pin is supported on PIN USR_IO[3:0] and register 0x0004 (General Purpose User Defined I/O Data Register). This is an input interface. Users can connect it to any real-time level-trigger signal output circuit for control or diagnostic purposes. For example, it can be used to detect the fan, temperature sensor, or other fault detect circuit.
7.31. LED Interfaces
The RTL8326 provides a flexible per-port LED display to show the per-port link status and diagnostic information. Both a parallel and serial interface are provided to drive the LEDs. During power on reset, the parallel LED signals are driven low and the serial interface shifts to a low value for about two seconds to turn on all the LEDs for testing purposes.
7.32. Parallel LED Interface
The parallel interface only provides a Gigabit port status LED and system status LED. LED signals include: LED_Glink#/ACT[1:0], LED_loopDet#, LED_BISTFail#, LED_EnTrunk[7:0]#.
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RTL8326 Datasheet
7.33. Serial LED Interface
The serial interface, SLED_CLK, and SLED_DATA provide clock and data to enable the external shift registers 74164 to capture the per-port link status and diagnostic information. Another pin, SLED_DMODE_CK, provides the diagnostic items selection control. Each pulse signal input from this pin changes the diagnostic item to be displayed on the diagnostic LED. Each port provides three port state LEDs (StateLED) and one diagnostic LED (DiagLED). The LED display type can be flexibly configured and can be enabled or disabled to achieve the optimal BOM cost. The LED display configuration is controlled by register 0x0005h `LED Display Configuration Register', and can also be configured via EEPROM. The StateLED display is defined by StatLED_mode[2:0] on register 0x0005. The available display types are shown in the following table.
Table 21. Serial LED Interface 001 010 011 100Spd Duplex Link/Act /Col /100Spd
StatLEDn_mode[2:0] StateLEDn Display Type
000 Link /Act
100 Duplex
101 Act
110 Link
111 Col
The display items of the diagnostic LED (DiagLED) are internally defined and are as follows: (DiagItem_0) DisablePort/RxError ON: Disabled port. Blinking: RX CRC error (DiagItem_1) FlowControl/FCActive ON: Flow control enabled. Blinking: Flow control active (DiagItem_2) TrunkPort/TKFault ON: Trunking enabled port. Blinking: Trunk fault warning (DiagItem_3) HighPriorityPort ON: High priority port (DiagItem_4) LoopDetectPort ON: Network loop connection fault detect (DiagItem_5) BroadcastStormAlarmPort ON: Broadcast Storm Alarm port (DiagItem_6) NULL Reserved for TX Utilization testing mode (DiagItem_7) NULL Reserved for RX Utilization testing mode The DiagLED display item is changed by a trigger signal input from hardware pin `SLED_DMODE_CK'. The change sequence order of the DiagLED is: DiagItem_0 DiagItem_1 DiagItem_2 ....... DiagItem_7 Loop to DiagItem_0
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7.33.1. Serial LED Display Panel Example (4 LEDs, Register 0x0005)
Enable serial LED display mode: set EnSerialMode: 1 Define the per-port 4 LED display mode: Configuration. set EnLED[3:0]: 1111 Define the statLED display type as: StatLED0=Link/Act, StatLED1=10/100M, StatLED2=Duplex/Collision: Configuration. set StatLED0_mode[2:0]=000, StatLED1_mode[2:0]=001, StatLED2_mode[2:0]=010 Follow the same method to configure the per-port 1 LED, per-port 2 LED, and per-port 3 LED display mode, with or without enabling the diagnostic LED. The LED panel is shown in Figure 17.
Diagnostic LED
DiagLED
Port State LED
StateLED 2 StateLED 1 StateLED 0 Port 0 Port 1 . . . . . . Port 25
8 7 6 5 4 3 2 1 0
NULL (Reserved) NULL (Reserved) Broadcast Storm Port Loop Detect Port High Priority Port TrunkPort /Fault FC/FC Active DisPort /RxErr
Diagnostics Indication LEDs
Figure 17. Serial LED Display
7.33.2. Serial LED Shift Out Sequence Order
The Serial LED output sequence is defined as follows: (first bit Each port has four LEDs. There are eight diagnostic LEDs: .... last bit).
[P0 StateLED0] [P0 StateLED1] [P0 StateLED2] [P0 DiagLED0] [P1 StateLED0] [P1 StateLED1] [P1 StateLED2] [P1 DiagLED0] - - - - - - -- - - - - - - - - - - -- - - - - - - - - - - -- - - - - - - - - - - -- - - - [P25 StateLED0] [P25 StateLED1] [P25 StateLED2] [P25 DiagLED0] [Reserved_(DiagS0)] [Reserved_(DiagS1)] [Reserved_(DiagS2)] [Reserved_(DiagS3)] [Reserved_(DiagS4)] [Reserved_(DiagS5)] [Reserved_(DiagS6)] [Reserved_(DiagS7)] 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller 53 Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
8.
Serial EEPROM Configuration (24LC024)
The EEPROM Configuration bits are directly mapped to some of the internal registers. For example, EEPROM addresses 0x00h and 0x01h directly map to internal register 0x0002 `RX IO PAD Delay Configuration'. The mapping rule is: EEPROM 0x00h: REG. 0x0002[7:0], EEPROM 0x01h: REG. 0x0002[15:8]
8.1. EEPROM Configuration vs. Internal Register Mapping Table
Table 22. EEPROM Configuration vs. Internal Register Mapping Table EEPROM Physical Address Description Corresponding Internal Register (8-Bit Data Entry) (24LC02) Address Mapping 0x 01~00 RX IO PAD Delay Configuration 0x0002 Bit[5:0] value MUST be 000000 (Bit 5 is used for BIST enable/disable of Control Point (CP) test) 0x 03~02 TX IO PAD Delay Configuration 0x0003 0x 05~04 LED Display Configuration 0x0005 0x 07~06 Reserved x 0x 09~08 Reserved x 0x 0B~0A Reserved x 0x 0D~0C Realtek Protocol Control 0x0200 0x 0F~0E RRCP security Mask Configuration 0 0x0201 0x 11~10 RRCP security Mask Configuration 1 0x0202 0x 13~12 Switch MAC ID 0 0x0203 0x 15~14 Switch MAC ID 1 0x0204 0x 17~16 Switch MAC ID 2 0x0205 0x 19~18 Chip Model ID 0x0206 0x 1B~1A Vender ID 0 0x0207 0x 1D~1C Vender ID 1 0x0208 0x 1F~1E Reserved x 0x 21~20 Reserved x 0x 23~22 ALT Configuration 0x0300 0x 25~24 Port Trunking Configuration 0x0307 0x 27~26 IGMP Snooping Control 0x0308 0x 29~28 VLAN Control 0x030B 0x 2B~2A Reserved x 0x 2D~2C Reserved x 0x 2F~2E QoS Control 0x0400 0x 31~30 Port Priority Configuration 0 0x0401 0x 33~32 Port Priority Configuration 1 0x0402 0x 35~34 Reserved x 0x 37~36 Reserved x 0x 39~38 Global Port Control Register 0x0607 0x 3B~3A Port Property Configuration 0 0x060A 0x 3D~3C Port Property Configuration 1 0x060B 0x 3F~3E Port Property Configuration 2 0x060C 0x 41~40 Port Property Configuration 3 0x060D 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller 54 Internal Default Value 0A80
0140 1E88 ---0000 0000 0000 0000 0000 0000 0000 0000 0000 --0004 0000 0000 0000 --0010 0000 0000 --0010 AFAF AFAF AFAF AFAF
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EEPROM Physical Address (8-Bit Data Entry) (24LC02) 0x 43~42 0x 45~44 0x 47~46 0x 49~48 0x 4B~4A 0x 4D~4C 0x 4F~4E 0x 51~50 0x 53~52 0x 55~54 0x 57~56 0x 58 ------- 0x 5f 0x 61~60 Description Corresponding Internal Register Address Mapping 0x060E 0x060F 0x0610 0x0611 0x0612 0x0613 0x0614 0x0615 0x0616 x x x 0xFFFF Internal Default Value AFAF AFAF AFAF AFAF AFAF AFAF AFAF AFAF BFBF ---0000
Port Property Configuration 4 Port Property Configuration 5 Port Property Configuration 6 Port Property Configuration 7 Port Property Configuration 8 Port Property Configuration 9 Port Property Configuration 10 Port Property Configuration 11 Port Property Configuration 12 Reserved Reserved Reserved Diagnostic Configuration purposes (must be configured as 0000)
9.
Internal Register Descriptions
Register Symbols: R: Read W: Write RW: Read/Write Note: Pin = Supports hardware pin strapping. EE = Supports EEPROM configuration.
9.1. System Configuration Registers
Register Base Address 0x0000 Offset 0 1 2 3 4 5 Table 23. System Configuration Registers Description RW System Reset Control Register. Switch Parameter Register. RX I/O PAD Delay Configuration. TX I/O PAD Delay Configuration. General Purpose User Define I/O Data Register. LED Display Configuration. W RW R R R RW Default 0 0480 0A80 0140 0 1E88 Pin EE
V V V V V
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9.2. System Status Registers
Register Base Address 0x0100 Offset 0 1 2 Table 24. System Status Registers Description Board Trapping Status Register. Loop Detect Status Register (32-bit). System Fault Indication Register. RW RW R R Default 0 0 0 Pin V EE
9.3. Management Configuration Registers
Register Base Address 0x0200 Offset 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 Table 25. Management Configuration Registers Description RW Realtek Protocol Control Register. RRCP Security Mask Configuration 0. RRCP Security Mask Configuration 1. Switch MAC ID Register 0. Switch MAC ID Register 1. Switch MAC ID Register 2. Chip Mode ID. System Vender ID Register 0. System Vender ID Register 1. RRCP Authentication Key Configuration Register. Port 0, 1 Bandwidth Control Register. Port 2, 3 Bandwidth Control Register. Port 4, 5 Bandwidth Control Register. Port 6, 7 Bandwidth Control Register. Port 8, 9 Bandwidth Control Register. Port 10, 11 Bandwidth Control Register. Port 12, 13 Bandwidth Control Register. Port 14, 15 Bandwidth Control Register. Port 16, 17 Bandwidth Control Register. Port 18, 19 Bandwidth Control Register. Port 20, 21 Bandwidth Control Register. Port 22, 23 Bandwidth Control Register. Port 24, 25 Bandwidth Control Register. RW RW RW R R R R R R R RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 2379 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin V EE V V V V V V V V V
9.4. Address Lookup Table (ALT) Control Register
Register Base Address 0x0300 Offset Table 26. Address Lookup Table (ALT) Control Register Description RW Default Pin EE
0 1 2 3 4 5
ALT Configuration Register. Address Learning Control Register 0. Address Learning Control Register 1. Unknown SA Capture Register 0. Unknown SA Capture Register 1. Unknown SA Capture Register 2. 56
RW RW RW R R R
0004 0 0 0 0 0
V
V
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Register Base Address Offset Description RW Default Pin EE
6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C
1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32
Unknown SA Status Register. Port Trunking Configuration Register. IGMP Snooping Control Register. IP Multicast Router Port Discovery Register (32-bit). Reserved. VLAN Control Register. Port VLAN ID Assignment Index Register 0 (Port 0, 1). Port VLAN ID Assignment Index Register 1 (Port 2, 3). Port VLAN ID Assignment Index Register 2 (Port 4, 5). Port VLAN ID Assignment Index Register 3 (Port 6, 7). Port VLAN ID Assignment Index Register 4 (Port 8, 9). Port VLAN ID Assignment Index Register 5 (Port 10, 11). Port VLAN ID Assignment Index Register 6 (Port 12, 13). Port VLAN ID Assignment Index Register 7 (Port 14, 15). Port VLAN ID Assignment Index Register 8 (Port 16, 17). Port VLAN ID Assignment Index Register 9 (Port 18, 19). Port VLAN ID Assignment Index Register 10 (Port 20, 21). Port VLAN ID Assignment Index Register 11 (Port 22, 23). Port VLAN ID Assignment Index Register 12 (Port 24, 25). VLAN Output Port Priority-tagging Control Register 0 (P#0~7). VLAN Output Port Priority-tagging Control Register 1 (P#8~15). VLAN Output Port Priority-tagging Control Register 2 (P#16~23). VLAN Output Port Priority-tagging Control Register 3 (P#24~25). VLAN Table Configuration Registers. VLAN_0_Entry_Configuration_0 (member[15:0]). VLAN_0_Entry_Configuration_1 (member[25:16]). VLAN_0_Entry_Configuration_2 (VID[11:0]). VLAN_1_Entry_Configuration_0 (member[15:0]). VLAN_1_Entry_Configuration_1 (member[25:16]). VLAN_1_Entry_Configuration_2 (VID[11:0]). VLAN_2_Entry_Configuration_0 (member[15:0]). VLAN_2_Entry_Configuration_1 (member[25:16]). VLAN_2_Entry_Configuration_2 (VID[11:0]). VLAN_3_Entry_Configuration_0 (member[15:0]). VLAN_3_Entry_Configuration_1 (member[25:16]). VLAN_3_Entry_Configuration_2 (VID[11:0]). VLAN_4_Entry_Configuration_0 (member[15:0]). VLAN_4_Entry_Configuration_1 (member[25:16]). VLAN_4_Entry_Configuration_2 (VID[11:0]). VLAN_5_Entry_Configuration_0 (member[15:0]). VLAN_5_Entry_Configuration_1 (member[25:16]). VLAN_5_Entry_Configuration_2 (VID[11:0]). VLAN_6_Entry_Configuration_0 (member[15:0]). VLAN_6_Entry_Configuration_1 (member[25:16]). VLAN_6_Entry_Configuration_2 (VID[11:0]). VLAN_7_Entry_Configuration_0 (member[15:0]). 57
R RW RW R -RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
0 0 0 0 -0 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 FFFF FFFF FFFF FFFF
V
V V
V
V
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
0001 0300 0000 0002 0300 0000 0004 0300 0000 0008 0300 0000 0010 0300 0000 0020 0300 0000 0040 0300 0000 0080
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Register Base Address Offset Description RW Default Pin EE
33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64
VLAN_7_Entry_Configuration_1 (member[25:16]). VLAN_7_Entry_Configuration_2 (VID[11:0]). VLAN_8_Entry_Configuration_0 (member[15:0]). VLAN_8_Entry_Configuration_1 (member[25:16]). VLAN_8_Entry_Configuration_2 (VID[11:0]). VLAN_9_Entry_Configuration_0 (member[15:0]). VLAN_9_Entry_Configuration_1 (member[25:16]). VLAN_9_Entry_Configuration_2 (VID[11:0]). VLAN_10_Entry_Configuration_0 (member[15:0]). VLAN_10_Entry_Configuration_1 (member[25:16]). VLAN_10_Entry_Configuration_2 (VID[11:0]). VLAN_11_Entry_Configuration_0 (member[15:0]). VLAN_11_Entry_Configuration_1 (member[25:16]). VLAN_11_Entry_Configuration_2 (VID[11:0]). VLAN_12_Entry_Configuration_0 (member[15:0]). VLAN_12_Entry_Configuration_1 (member[25:16]). VLAN_12_Entry_Configuration_2 (VID[11:0]). VLAN_13_Entry_Configuration_0 (member[15:0]). VLAN_13_Entry_Configuration_1 (member[25:16]). VLAN_13_Entry_Configuration_2 (VID[11:0]). VLAN_14_Entry_Configuration_0 (member[15:0]). VLAN_14_Entry_Configuration_1 (member[25:16]). VLAN_14_Entry_Configuration_2 (VID[11:0]). VLAN_15_Entry_Configuration_0 (member[15:0]). VLAN_15_Entry_Configuration_1 (member[25:16]). VLAN_15_Entry_Configuration_2 (VID[11:0]). VLAN_16_Entry_Configuration_0 (member[15:0]). VLAN_16_Entry_Configuration_1 (member[25:16]). VLAN_16_Entry_Configuration_2 (VID[11:0]). VLAN_17_Entry_Configuration_0 (member[15:0]). VLAN_17_Entry_Configuration_1 (member[25:16]). VLAN_17_Entry_Configuration_2 (VID[11:0]). VLAN_18_Entry_Configuration_0 (member[15:0]). VLAN_18_Entry_Configuration_1 (member[25:16]). VLAN_18_Entry_Configuration_2 (VID[11:0]). VLAN_19_Entry_Configuration_0 (member[15:0]). VLAN_19_Entry_Configuration_1 (member[25:16]). VLAN_19_Entry_Configuration_2 (VID[11:0]). VLAN_20_Entry_Configuration_0 (member[15:0]). VLAN_20_Entry_Configuration_1 (member[25:16]). VLAN_20_Entry_Configuration_2 (VID[11:0]). VLAN_21_Entry_Configuration_0 (member[15:0]). VLAN_21_Entry_Configuration_1 (member[25:16]). VLAN_21_Entry_Configuration_2 (VID[11:0]). VLAN_22_Entry_Configuration_0 (member[15:0]). VLAN_22_Entry_Configuration_1 (member[25:16]). VLAN_22_Entry_Configuration_2 (VID[11:0]). VLAN_23_Entry_Configuration_0 (member[15:0]). VLAN_23_Entry_Configuration_1 (member[25:16]). VLAN_23_Entry_Configuration_2 (VID[11:0]). 58
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
0300 0000 0100 0300 0000 0200 0300 0000 0400 0300 0000 0800 0300 0000 1000 0300 0000 2000 0300 0000 4000 0300 0000 8000 0300 0000 0000 0301 0000 0000 0302 0000 0000 0304 0000 0000 0308 0000 0000 0310 0000 0000 0320 0000 0000 0340 0000 0000 0380 0000
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Register Base Address Offset Description RW Default Pin EE
65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C
VLAN_24_Entry_Configuration_0 (member[15:0]). VLAN_24_Entry_Configuration_1 (member[25:16]). VLAN_24_Entry_Configuration_2 (VID[11:0]). VLAN_25_Entry_Configuration_0 (member[15:0]). VLAN_25_Entry_Configuration_1 (member[25:16]). VLAN_25_Entry_Configuration_2 (VID[11:0]). VLAN_26_Entry_Configuration_0 (member[15:0]). VLAN_26_Entry_Configuration_1 (member[25:16]). VLAN_26_Entry_Configuration_2 (VID[11:0]). VLAN_27_Entry_Configuration_0 (member[15:0]). VLAN_27_Entry_Configuration_1 (member[25:16]). VLAN_27_Entry_Configuration_2 (VID[11:0]). VLAN_28_Entry_Configuration_0 (member[15:0]). VLAN_28_Entry_Configuration_1 (member[25:16]). VLAN_28_Entry_Configuration_2 (VID[11:0]). VLAN_29_Entry_Configuration_0 (member[15:0]). VLAN_29_Entry_Configuration_1 (member[25:16]). VLAN_29_Entry_Configuration_2 (VID[11:0]). VLAN_30_Entry_Configuration_0 (member[15:0]). VLAN_30_Entry_Configuration_1 (member[25:16]). VLAN_30_Entry_Configuration_2 (VID[11:0]). VLAN_31_Entry_Configuration_0 (member[15:0]). VLAN_31_Entry_Configuration_1 (member[25:16]). VLAN_31_Entry_Configuration_2 (VID[11:0]).
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
FFFF 03FF 0000 FFFF 03FF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
9.5. Queue Control Registers
Register Base Address 0x0400 Offset 0 1 2 Table 27. Queue Control Registers Description QoS Control Register. Port Priority Configuration Register 0. Port Priority Configuration Register 1. RW RW RW RW Default 0010 0 0 Pin V V EE V V V
9.6. PHY Access Control Register
Register Base Address 0x0500 Offset 0 1 2 Table 28. PHY Access Control Register Description PHY Access Control Register. PHY Access Write Data Register. PHY Access Read Data Register. RW RW RW R Default 0 0 0 Pin EE
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9.7. Port Control Registers
Table 29. Port Control Registers Register Base Address 0x0600 Offset 0~6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17~18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 Description Reserved. Global Port Control Register. Port Disable Control Register 0. Port Disable Control Register 1. Port Property Configuration Register 0 (Port 0, 1). Port Property Configuration Register 1 (Port 2, 3). Port Property Configuration Register 2 (Port 4, 5). Port Property Configuration Register 3 (Port 6, 7). Port Property Configuration Register 4 (Port 8, 9). Port Property Configuration Register 5 (Port 10, 11). Port Property Configuration Register 6 (Port 12, 13). Port Property Configuration Register 7 (Port 14, 15). Port Property Configuration Register 8 (Port 16, 17). Port Property Configuration Register 9 (Port 18, 19). Port Property Configuration Register 10 (Port 20, 21). Port Property Configuration Register 11 (Port 22, 23). Port Property Configuration Register 12 (Port 24, 25). Reserved. Port Link Status Register 0 (Port 0, 1). Port Link Status Register 1 (Port 2, 3). Port Link Status Register 2 (Port 4, 5). Port Link Status Register 3 (Port 6, 7). Port Link Status Register 4 (Port 8, 9). Port Link Status Register 5 (Port 10, 11). Port Link Status Register 6 (Port 12, 13). Port Link Status Register 7 (Port 14, 15). Port Link Status Register 8 (Port 16, 17). Port Link Status Register 9 (Port 18, 19). Port Link Status Register 10 (Port 20, 21). Port Link Status Register 11 (Port 22, 23). Port Link Status Register 12 (Port 24, 25). RW -RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW -R R R R R R R R R R R R R Default -0010 0 0 AFAF AFAF AFAF AFAF AFAF AFAF AFAF AFAF AFAF AFAF AFAF AFAF BFBF -0 0 0 0 0 0 0 0 0 0 0 0 0 Pin EE
V
V
V V V V V V V V V V V V V
9.8. MIB Counter Registers
Table 30. MIB Counter Registers Register Base Address 0x0700 Offset Description RW Default Pin EE
0 1 2 3 4 5 6 7
Port MIB Counter Object Selection Register 0 (Port 0, 1). Port MIB Counter Object Selection Register 1 (Port 2, 3). Port MIB Counter Object Selection Register 2 (Port 4, 5). Port MIB Counter Object Selection Register 3 (Port 6, 7). Port MIB Counter Object Selection Register 4 (Port 8, 9). Port MIB Counter Object Selection Register 5 (Port 10, 11). Port MIB Counter Object Selection Register 6 (Port 12, 13). Port MIB Counter Object Selection Register 7 (Port 14, 15). 60
RW RW RW RW RW RW RW RW
0555 0555 0555 0555 0555 0555 0555 0555
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Register Base Address Offset Description RW Default Pin EE
8 9 A B C
Port MIB Counter Object Selection Register 8 (Port 16, 17). Port MIB Counter Object Selection Register 9 (Port 18, 19). Port MIB Counter Object Selection Register 10 (Port 20, 21). Port MIB Counter Object Selection Register 11 (Port 22, 23). Port MIB Counter Object Selection Register 12 (Port 24, 25).
RW RW RW RW RW
0555 0555 0555 0555 0555
9.8.1.
Register Base Address 0x0700
Port MIB Counter 1 Register (RX Counter) (32-bits)
Offset Table 31. Port MIB Counter 1 Register (RX Counter) (32-bits) Description RW Default Pin EE
D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26
Port 0 MIB Counter 1 Register (RX Counter) (32-bits). Port 1 MIB Counter 1 Register (RX Counter) (32-bits). Port 2 MIB Counter 1 Register (RX Counter) (32-bits). Port 3 MIB Counter 1 Register (RX Counter) (32-bits). Port 4 MIB Counter 1 Register (RX Counter) (32-bits). Port 5 MIB Counter 1 Register (RX Counter) (32-bits). Port 6 MIB Counter 1 Register (RX Counter) (32-bits). Port 7 MIB Counter 1 Register (RX Counter) (32-bits). Port 8 MIB Counter 1 Register (RX Counter) (32-bits). Port 9 MIB Counter 1 Register (RX Counter) (32-bits). Port 10 MIB Counter 1 Register (RX Counter) (32-bits). Port 11 MIB Counter 1 Register (RX Counter) (32-bits). Port 12 MIB Counter 1 Register (RX Counter) (32-bits). Port 13 MIB Counter 1 Register (RX Counter) (32-bits). Port 14 MIB Counter 1 Register (RX Counter) (32-bits). Port 15 MIB Counter 1 Register (RX Counter) (32-bits). Port 16 MIB Counter 1 Register (RX Counter) (32-bits). Port 17 MIB Counter 1 Register (RX Counter) (32-bits). Port 18 MIB Counter 1 Register (RX Counter) (32-bits). Port 19 MIB Counter 1 Register (RX Counter) (32-bits). Port 20 MIB Counter 1 Register (RX Counter) (32-bits). Port 21 MIB Counter 1 Register (RX Counter) (32-bits). Port 22 MIB Counter 1 Register (RX Counter) (32-bits). Port 23 MIB Counter 1 Register (RX Counter) (32-bits). Port 24 MIB Counter 1 Register (RX Counter) (32-bits). Port 25 MIB Counter 1 Register (RX Counter) (32-bits).
R R R R R R R R R R R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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9.8.2.
Register Base Address 0x0700
Port MIB Counter 2 Register (TX Counter) (32-bits)
Offset Table 32. Port MIB Counter 2 Register (TX Counter) (32-bits) Description RW Default Pin EE
27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40
Port 0 MIB Counter 2 Register (TX Counter) (32-bits). Port 1 MIB Counter 2 Register (TX Counter) (32-bits). Port 2 MIB Counter 2 Register (TX Counter) (32-bits). Port 3 MIB Counter 2 Register (TX Counter) (32-bits). Port 4 MIB Counter 2 Register (TX Counter) (32-bits). Port 5 MIB Counter 2 Register (TX Counter) (32-bits). Port 6 MIB Counter 2 Register (TX Counter) (32-bits). Port 7 MIB Counter 2 Register (TX Counter) (32-bits). Port 8 MIB Counter 2 Register (TX Counter) (32-bits). Port 9 MIB Counter 2 Register (TX Counter) (32-bits). Port 10 MIB Counter 2 Register (TX Counter) (32-bits). Port 11 MIB Counter 2 Register (TX Counter) (32-bits). Port 12 MIB Counter 2 Register (TX Counter) (32-bits). Port 13 MIB Counter 2 Register (TX Counter) (32-bits). Port 14 MIB Counter 2 Register (TX Counter) (32-bits). Port 15 MIB Counter 2 Register (TX Counter) (32-bits). Port 16 MIB Counter 2 Register (TX Counter) (32-bits). Port 17 MIB Counter 2 Register (TX Counter) (32-bits). Port 18 MIB Counter 2 Register (TX Counter) (32-bits). Port 19 MIB Counter 2 Register (TX Counter) (32-bits). Port 20 MIB Counter 2 Register (TX Counter) (32-bits). Port 21 MIB Counter 2 Register (TX Counter) (32-bits). Port 22 MIB Counter 2 Register (TX Counter) (32-bits). Port 23 MIB Counter 2 Register (TX Counter) (32-bits). Port 24 MIB Counter 2 Register (TX Counter) (32-bits). Port 25 MIB Counter 2 Register (TX Counter) (32-bits).
R R R R R R R R R R R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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9.8.3.
Register Base Address 0x0700
Port MIB Counter 3 Register (Diagnostic Counter) (32-bits)
Offset Table 33. Port MIB Counter 3 Register (Diagnostic Counter) (32-bits) Description RW Default Pin EE
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A
Port 0 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 1 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 2 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 3 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 4 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 5 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 6 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 7 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 8 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 9 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 10 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 11 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 12 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 13 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 14 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 15 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 16 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 17 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 18 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 19 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 20 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 21 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 22 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 23 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 24 MIB Counter 3 Register (Diagnostic Counter) (32-bits). Port 25 MIB Counter 3 Register (Diagnostic Counter) (32-bits).
R R R R R R R R R R R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9.9. System Parameter Register (Reserved)
Register Base Address 0xFFFF Offset -Table 34. System Parameter Register (Reserved) Description RW System Parameter Register (Reserved). RW Default 0 Pin V EE V
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10.
Internal Register Settings
LL: LH: SC: RC: Latch Low until cleared Latch High until cleared Self Clearing Read to Clear
Register Symbols: R: Read W: Write RW: Read/Write
10.1. System Configuration Register
10.1.1. 0x0000H: System Reset Control Register
Bits 0 Name SRST Table 35. 0x0000H: System Reset Control Register Description Soft Reset. A soft reset will reset the system similar to a power on reset except that the user configuration will not be cleared: 1. The MAC table and VLAN table data will be kept. 2. All current user configured internal register values will be kept. 3. The EEPROM download will not be done again. 4. The system will restart the auto-negotiation process. 0: Normal 1: Soft reset Hardware Reset. Resets the system to the power on initial state: 1. Downloads configuration from strap pin and EEPROM. 2. Starts internal Memory self test. 3. Clears all the MAC, VLAN tables. 4. Resets all registers to default values. 5. Restarts auto-negotiation. 0: Normal 1: Hardware reset RW W/SC Default 0
1
HRST
W/SC
0
15:2
Reserved
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10.1.2. 0x0001H: Switch Parameter Register
Note: The Write operation is reserved for IC testing mode. Do NOT write this register.
Bits 1:0 Name MaxPktLen[1:0] Table 36. 0x0001H: Switch Parameter Register Description System Valid Max Packet Length. The minimum packet length is 64 bytes. The maximum packet length is controlled by MaxPktLen[1:0]: 00: 1536 bytes (Default) 01: 1552 byte 1x: Reserved. Transmit IPG Compensation. Used to compensate the oscillator frequency or incoming packet Inter-Packet Gap (IPG) tolerance. 0: Give +65 ppm TXIPG compensation (Default) 1: Give +90 ppm TXIPG compensation Max Pause Count for Congestion Control. 0: Supports a maximum of 128 Pause frames during congestion control (Default) 1: Continue Pause mode. Do not limit the Pause frame count during congestion control. Disable Back pressure 48 Pass One Algorithm. When the 48One algorithm is enabled, the switch will pass one incoming packet after every 48 collisions. 0: Enable 48 Pass One algorithm (Default) 1: Disable 48 Pass One algorithm This is a system test bit. Enable congested Packet Drop after over per-port flow control threshold 24 buffer page. When disabled, it allows reception of incoming packets until the output queue is full. 0: Disable (Default) 1: Enable Enable Carrier Based Back Pressure Mode. Half duplex back pressure algorithm selection. 0: Select Collision based back pressure mode 1: Select Carrier based back pressure mode (Default) Disable Back Off Timer BIST. 0: Enable Back Off Timer BIST (Built-In Self Test) 1: Disable Back Off Timer BIST Speed Up Back Off Timer 0: Normal timer (Default) 1: Speed up timer Enable Advanced Back Pressure Back Off scheme. 0: Normal mode 1: Advanced mode; k: min (n, 3) Reserved for Port Descriptor Threshold Tuning Control Testing. Keep the value at 00. RW RW Default HW pin
MaxPktLen[1:0]
2
TXIPG_Comp
RW
HW pin TXIPG_Comp
3
MaxPauseCnt
RW
HW pin MaxPauseCnt
4
DisBKP48One
RW
HW pin DisBKP48One
5 6
SWTest En24Drop
RW RW
0 HW pin En24Drop
7
EnCRSBKPMode
RW
HW pin EnCRSBKPmode
8
DisBkOffBIST
RW
0
9
SpdBkOff
RW
HW pin EnSpdBkOff 1
10
EnBKPBkOff3
RW
12:11
PortDscThr[1:0]
RW
00
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Bits 14:13 Name
GlobalDscThr[1:0]
15
SpeedUp
Description Reserved for Global Descriptor Threshold Tuning Control Testing purposes only. Keep the value at 00. Reserved for Speed Up Internal BIST Clock for Control Point (CP) Testing. Keep the value at 0.
RW RW
Default 00
RW
HW pin EnSPDUP
10.1.3. 0x0002H: RX I/O PAD Delay Configuration
Bits 4:0 Table 37. 0x0002H: RX I/O PAD Delay Configuration Name Description Reserved Reserved bits. (EEPROM check) Used for EEPROM existence checking. Keep the value at 000000. DisBIST Reserved for engineering test mode. 0: Enable BIST 1: Disable BIST Keep the value at 0. RxDelayF0_Cfg[1:0] Fast Ethernet Port 0~7 SMII RX I/O PAD input delay Configuration. 00: Delay 0 ns (Default) 01: Delay 1 ns 10: Delay 2 ns (Recommend) 11: Delay 3 ns RxDelayF1_Cfg[1:0] Fast Ethernet Port 8~15 SMII RX I/O PAD input delay Configuration. 00: Delay 0 ns (Default) 01: Delay 1 ns 10: Delay 2 ns (Recommend) 11: Delay 3 ns RxDelayF2_Cfg[1:0] Fast Ethernet Port 16~23 SMII RX I/O PAD input delay Configuration. 00: Delay 0 ns (Default) 01: Delay 1 ns 10: Delay 2 ns (Recommend) 11: Delay 3 ns RxDelayG0_Cfg[1:0] Gigabit Port G0 GMII RX I/O PAD input delay Configuration. 00: Delay 0 ns (Default) 01: Delay 1 ns 10: Delay 2 ns 11: Delay 3 ns RxDelayG1_Cfg[1:0] Gigabit Port G1 GMII RX I/O PAD input delay Configuration. 00: Delay 0 ns (Default) 01: Delay 1 ns 10: Delay 2 ns 11: Delay 3 ns RW R Default 0
5
R (W: EEPROM)
0
7:6
R HW pin. (W: EEPROM) OCT0_RXD _Delay_2ns
9:8
R HW pin. (W: EEPROM) OCT1_RXD _Delay_2ns
11:10
R HW pin. (W: EEPROM) OCT2_RXD _Delay_2ns
13:12
R (W: EEPROM)
00
15:14
R (W: EEPROM)
00
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10.1.4. 0x0003H: TX I/O PAD Delay Configuration
Bits 5:0 7:6 Table 38. 0x0003H: TX I/O PAD Delay Configuration Name Description Reserved TxDealyG0_Cfg[1:0] Gigabit Port G0 GMII TX I/O PAD output delay Configuration. 00: Delay 0 ns 01: Delay 1 ns (Default) 10: Delay 2 ns 11: Delay 3 ns TxDealyG1_Cfg[1:0] Gigabit Port G1 GMII TX I/O PAD output delay Configuration. 00: Delay 0 ns 01: Delay 1 ns (Default) 10: Delay 2 ns 11: Delay 3 ns TxDelayRefClk0 Fast Ethernet Port 0~7 SMII REFCLK I/O PAD output delay Configuration. 0: Delay 0 ns (Default) 1: Delay 2 ns TxDelayRefClk1 Fast Ethernet Port 8~15 SMII REFCLK I/O PAD output delay Configuration. 0: Delay 0 ns (Default) 1: Delay 2 ns TxDelayRefClk2 Fast Ethernet Port 16~23 SMII REFCLK I/O PAD output delay Configuration. 00: Delay 0 ns (Default) 01: Delay 1 ns Reserved RW R (W: EEPROM) Default 01
9:8
R (W: EEPROM)
01
10
R (W: EEPROM)
0
11
R (W: EEPROM)
0
12
R (W: EEPROM)
0
15:13
10.1.5. 0x0004H: General Purpose User Defined I/O Data Register
Bits 3:0 Table 39. 0x0004H: General Purpose User Defined I/O Data Register Name Description RW USR_IOD[3:0] User Defined I/O Data. R These bits reflect the real time value of the hardware pin USR_IO[3:0]. Reserved Default HW pin:
USR_IOD[3:0]
15:4
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10.2. 0x0005H: LED Display Configuration
Bits 2:0 Table 40. 0x0005H: LED Display Configuration Description Mode Selection for State LED0. This state LED mode selection register controls the status type of the State LED0. The Status type is defined as follows: 000: Link/Act (Default) 001: 100Spd 010: Duplex/Col 011: Link/Act/100Spd 100: Duplex 101: Act 110: Link 111: Col StatLED1_mode[2:0] Mode Selection for State LED1. 000: Link/Act (Default) 001: 100Spd 010: Duplex/Col 011: Link/Act/100Spd 100: Duplex 101: Act 110: Link 111: Col StatLED2_mode[2:0] Mode Selection for State LED2. 000: Link/Act (Default) 001: 100Spd 010: Duplex/Col 011: Link/Act/100Spd 100: Duplex 101: Act 110: Link 111: Col EnLED[3:0] State LED 0,1,2 and Diagnostic LED Enable/Disable Control. EnLED[3:0] controls enabling/disabling of DiagLED, StatLED2, StatLED1, StatLED0. 0: Disable 1: Enable If an LED is disabled, the corresponding serial clock will be masked. Reserved EnSerialMode Serial/Parallel LED Display Mode Configuration. Two LED output display modes are supported; parallel mode and serial mode. 0: Parallel LED mode 1: Serial LED mode Name StatLED0_mode[2:0] RW RW Default 000
5:3
RW
001
8:6
RW
010
12:9
RW
1111
14:13 15
RW
0
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10.3. System Status Register
10.3.1. 0x0100H: Board Trapping Status Register
Bits 0 Table 41. 0x0100H: Board Trapping Status Register Name Description EEPROM_detect_ EEPROM Existence Status. status 0: Exists 1: Does not Exist EnGDSRev Enable Gigabit Port GMII/TBI TXD[7:0] Sequence Reverse. When set, reverses the sequence of GMII/TBI TXD `[7:0]' to `[0:7]'. Note: RXD[7:0] keeps the original sequence. 0: Disable (Default) 1: Enable (Reverses the sequence) FrcTBIMode[1:0] Force Enable Gigabit port at TBI Mode Interface of Port G0 or G1. Bit FrcTBImode[0], control Gigabit port 0 Bit FrcTBImode[1], control Gigabit port 1 0: Force enable GMII/MII Mode Interface (Default) 1: Force enable TBI Mode Interface Reserved RW R Default -
1
RW
HW pin. EnGDSRev
3:2
RW
HW pin. FrcTBIMode [1:0]
15:4
10.3.2. 0x0101H: Loop Detect Status Register (32-Bit Register)
Bits 25:0 Table 42. 0x0101H: Loop Detect Status Register (32-Bit Register) Name Description RW R LoopDetPort[25:0] Network Loop event Detect Port Status. If the loop detect function is enabled, the corresponding bit of LoopDetPort[25:0] will be set whenever a loop event is detected on the corresponding switch port. The set bit is cleared only when the loop event has disappeared on that port. When the loop detect function is enabled, the switch will periodically transmit one loop detect diagnostic frame. The normal interval time is approx. five minutes. When a loop event is detected the interval time will be changed to fast mode. In fast mode the interval time is about 1 second in order to accelerate detection and diagnostic. The loop event will be reported in this Loop Detect Status Register. 0: No Loop detected on this port 1: Loop detected on this port 31:26 Reserved Default 0
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10.3.3. 0x0102H: System Fault Indication Register
Bits 0 1 Name BTest TrunkFault Table 43. 0x0102H: System Fault Indication Register Description A system test bit. Trunk Fault event flag. The flag indicates that there is a trunk port member link down. The trunk will still continue to operate due to the trunk auto fault recovery algorithm. 0: No trunk fault detected 1: Trunk fault detected Network Loop Fault Indication. When the Loop Fault indication is set, a loop detected port will be reported on the Loop Detect Port Register. 0: Network Loop not detected 1: Network Loop detected Gigabit PHY existence report for Gigabit Port G1, G0. 0: Exists 1: Does not exist The Fault Trunk Group Indication. Indicates a Link Fault in the trunk group. A physical link failure of an enabled trunk group will cause the corresponding bit to be set in the FaultTkGroup[7:0]. This is a real time fault status report. Even though the Trunk Group's fault occurred and the fault bit is set, the corresponding trunk can still work properly as fault recovery will be auto applied. FaultTkGroup[0] indicator for Trunk 0: (port 0, 1) FaultTkGroup[1] indicator for Trunk 1: (port 2, 3) FaultTkGroup[2] indicator for Trunk 2: (port 4, 5, 6, 7) FaultTkGroup[3] indicator for Trunk 3: (port 8, 9, 10, 11) FaultTkGroup[4] indicator for Trunk 4: (port 12, 13, 14, 15) FaultTkGroup[5] indicator for Trunk 5: (port 16, 17, 18, 19) FaultTkGroup[6] indicator for Trunk 6: (port 20, 21, 22, 23) FaultTkGroup[7] indicator for Trunk 7: (port G0, G1) 0: Trunk OK 1: Trunk Fault detected 15:10 Reserved RW R R Default 000 0
2
LoopFault
R
0
4:3
GigaPHY_ NotExist[1:0] FaultTkGroup[7:0]
R
0
12:5
R
00000000
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10.4. Management Configuration Register
10.4.1. 0x0200H: Realtek Protocol Control Register
Bits 0 Name DisRRCP Table 44. 0x0200H: Realtek Protocol Control Register Description Disable Realtek Remote Control Protocol (RRCP). 0: Enable RRCP (Default) 1: Disable RRCP Disable Realtek Remote Echo Protocol. 0: Enable REcho protocol (Default) 1: Disable REcho protocol Enable Loop Detect Function. When enabled, the loop detect status will be reported in register 0x0101 (Loop Detect Status Register). 0: Disable 1: Enable RW RW Default HW pin: DisRRCP HW pin. DisREcho HW pin. EnLoopDet
1
DisREcho
RW
2
EnLoopDet
RW
15:3
Reserved
10.4.2. 0x0201H: RRCP Security Mask Configuration Register 0
Bits 15:0 Table 45. 0x0201H: RRCP Security Mask Configuration Register 0 Name Description RW RW RRCP_SMask[15:0] RRCP Management Security Mask Configuration. Configuration for ports 0 to 15. Specifies which port's incoming RRCP access commands will be responded to. 0: RRCP Access enabled port 1: RRCP Access disabled port Note: Ports 0~23 RRCP security mask will be set if the hardware strap pin EnHomeVlan is pulled high during power on reset. This can be over written by EEPROM or registers access. Default 0
10.4.3. 0x0202H: RRCP Security Mask Configuration Register 1
Bits 9:0 Table 46. 0x0202H: RRCP Security Mask Configuration Register 1 Name Description RW RW RRCP_SMask[25:16] RRCP Management Security Mask Configuration. Configuration for ports 16 to 25.0. Specifies which port's incoming RRCP access commands will be responded to. 0: RRCP Access enabled port 1: RRCP Access disabled port Note: Ports 0~23 RRCP security mask will be set if the hardware strap pin EnHomeVlan is pulled high during power on reset. This can be over written by EEPROM or register access. Default 0
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10.4.4. 0x0203H: Switch MAC ID Register 0
Bits 15:0 Name MACID[15:0] Table 47. 0x0203H: Switch MAC ID Register 0 Description Switch Physical MAC Address bit[15:0]. Bitmap example. For a given 48-bit MAC address `52-54-4C-01-02-03', then MACID[15:0]=54-52. RW R (W: EEPROM) Default 0
10.4.5. 0x0204H: Switch MAC ID Register 1
Bits 15:0 Name MACID[31:16] Table 48. 0x0204H: Switch MAC ID Register 1 Description Switch Physical MAC Address bit[31:16] Bitmap example. For a given 48-bit MAC address `52-54-4C-01-02-03', then MACID[31:16]=01-4C. RW R (W: EEPROM) Default 0
10.4.6. 0x0205H: Switch MAC ID Register 2
Bits 15:0 Name MACID[47:32] Table 49. 0x0205H: Switch MAC ID Register 2 Description Switch Physical MAC Address bit[47:32]. Bitmap example. For a given 48-bit MAC address `52-54-4C-01-02-03', then MACID[47:32]=03-02. RW R (W: EEPROM) Default 0
10.4.7. 0x0206H: Chip Model ID
Bits 7:0 Name ChipID[7:0] Table 50. 0x0206H: Chip Model ID Description Chip ID. Identifies the chip version for programmer version control. RW R (W: EEPROM) Default 0
15:8
Reserved
10.5. 0x0207H: System Vender ID Register 0
Bits 15:0 Name VenderID[15:0] Table 51. 0x0207H: System Vender ID Register 0 Description System Vender Identity Stream [15:0]. Used for the system vender to fill a code or name stream for switch device model number or vender name identification. RW R (W: EEPROM) Default 0
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10.6. 0x0208H: System Vender ID Register 1
Bits 15:0 Name VenderID[31:16] Table 52. 0x0208H: System Vender ID Register 1 Description System Vender Identity Stream [31:16]. Used for system vender to fill a code or name stream for switch device model number or vender name identification. RW R (W: EEPROM) Default 0
10.7. 0x0209H: RRCP Authentication Key Configuration Register
Bits 15:0 Table 53. 0x0209H: RRCP Authentication Key Configuration Register Name Description RW RW RRCP_KEY[15:0] RRCP Access Authentication Key Configuration. After power on reset, the RRCP Authentication Key is set to the default value `0x2379'. It can be updated via the CPU interface or by an RRCP control frame with a correct current authentication key value in the frame. The Authentication Key checking rule for RRCP frames is defined as follows: 1. For the Hello command frame: -- Broadcast Hello frame: Do not check Auth. Key. -- Unicast Hello frame: Auth. Key = RRCP_KEY[15:0] Note: When the RRCP_KEY[15:0] is updated by the user, only unicast Hello frames are valid. 2. For a Get/Set command frame: Always uses the current key value defined by RRCP_KEY[15:0] Default 0x2379
10.8. 0x020AH: Port 0, 1 Bandwidth Control Register
Bits 3:0 Name P0RXRate[3:0] Table 54. 0x020AH: Port 0, 1 Bandwidth Control Register Description Port 0 RX Bandwidth Control. Configures the maximum output bandwidth of the port. Bit 3 is a reserved bit. Bit[2:0] controls the maximum RX rate of the port. 000: Disables rate control 001: 128Kbps 010: 256Kbps 011: 512Kbps 100: 1Mbps 101: 2Mbps 110: 4Mbps 111: 8Mbps RW RW Default 0000
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Bits 7:4 Name P0TXRate[3:0] Description Port 0 TX Bandwidth Control. Configures the maximum input bandwidth of the port. Bit 3 is a reserved bit. Bit[2:0] controls the maximum TX rate of the port. 000: Disables rate control 001: 128Kbps 010: 256Kbps 011: 512Kbps 100: 1Mbps 101: 2Mbps 110: 4Mbps 111: 8Mbps Port 1 RX Bandwidth Control Configures the maximum output bandwidth of the port. Bit 3 is a reserved bit. Bit[2:0] controls the maximum RX rate of the port. 000: Disables rate control 001: 128Kbps 010: 256Kbps 011: 512Kbps 100: 1Mbps 101: 2Mbps 110: 4Mbps 111: 8Mbps Port 1 TX Bandwidth Control Configures the maximum input bandwidth of the port. Bit 3 is a reserved bit. Bit[2:0] controls the maximum TX rate of the port. 000: Disables rate control 001: 128Kbps 010: 256Kbps 011: 512Kbps 100: 1Mbps 101: 2Mbps 110: 4Mbps 111: 8Mbps RW RW Default 0000
11:8
P1RXRate[3:0]
RW
0000
15:12
P1TXRate[3:0]
RW
0000
10.8.1. 0x020BH ~ 0x0216H: Port 2 ~ 25 Bandwidth Control Register
Refer to Table 54, page 73, for Configuration description of n: 1 ~ 12.
Bits 3:0 7:4 11:8 15:12 Table 55. 0x020BH ~ 0x0216H: Port 2 ~ 25 Bandwidth Control Register Name Description RW P2nRXRate[3:0] Port 2n RX Bandwidth Control. RW P2nTXRate[3:0] Port 2n TX Bandwidth Control. RW P2n+1RXRate[3:0] Port 2n+1 RX Bandwidth Control. RW P2n+1TXRate[3:0] Port 2n+1 TX Bandwidth Control. RW Default 0000 0000 0000 0000
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10.9. Address Lookup Table (ALT) Control Register
10.9.1. 0x0300H: ALT Configuration Register
Bits 0 Name DisMacAging Table 56. 0x0300H: ALT Configuration Register Description Global Disable Mac Table Aging Function. 0: Enable Aging function (Default) 1: Disable Aging function Enable Fast Aging Time Mode. 0: Disable Fast Aging time; 300 seconds (Default) 1: Enable Fast Aging time; 12 seconds Global Enable 802.1D Specified Reserved Control Frame Filtering. When network control packets are received with a destination MAC address as the group MAC address: (01-80-C2-00-00-03 ~ 01-80-C2-00-00-0F), the switch will drop the packets if the bit EnCtrlFilter=1. Otherwise (EnCtrlFilter=0) they will be flooded. 1: Enable Filtering (Default) 0: Disable Filtering Global Enable Drop Unknown Destination MAC address (DA) packet. If drop unknown DA is disabled, packets with an unknown DA will be flooded. If drop unknown DA is enabled, packets with an unknown DA will be dropped. 0: Disable Drop Unknown DA 1: Enable Drop Unknown DA RW RW Default 0
1
EnFastAgeTime
RW
HW pin. EnFastAge HW pin. EnCtrlFFilter
2
EnCtrlFFilter
RW
3
EnDropUknDA
RW
0
15:4
Reserved
10.9.2. 0x0301H: Address Learning Control Register 0
Bits 15:0 Table 57. 0x0301H: Address Learning Control Register 0 Name Description DisMacLearn[15:0] Per-Port Disable Mac Address Learning Function (Ports 0~15). DisMacLearn[15:0] control port[15:0]. The Layer 2 MAC address learning function can be per-port disabled for security management purposes. Generally this register is used with the ALT Configuration Register (0x0300) bits `DisMacAging' & `EnDropUknDA'. 0: Enable learning (Default) 1: Disable learning RW RW Default 0
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10.9.3. 0x0302H: Address Learning Control Register 1
Bits 9:0 Table 58. 0x0302H: Address Learning Control Register 1 Name Description DisMacLearn[25:16] Per-Port Disable Mac Address Learning Function (port 16~25). DisMacLearn[25:16] control port[25:16]. The Layer 2 MAC address learning function can be per-port disabled for security management purposes. Generally this register is used with the ALT Configuration Register (0x0300H) bits `DisMacAging' & `EnDropUknDA'. 0: Enable learning (Default) 1: Disable learning Reserved RW RW Default 0
15:10
10.9.4. 0x0303H: Unknown SA Capture Register 0
Bits 15:0 Table 59. 0x0303H: Unknown SA Capture Register 0 Name Description UnknownSA[15:0] Unknown Source MAC Address Capture (Byte 0, 1). Registers 0, 1, and 2 are used to capture unknown Source MAC addresses for MAC table address security management. When a port's MAC address learning function is disabled (locked), then any incoming Source MAC address from this port that has not been learned on the MAC table will be captured into the Unknown SA Management Register 0, 1, 2. Only the first detected unknown SA can be captured until the unknownSAPID register has been read. The unknown Source MAC address will be captured into Register addresses 0x0303 ~ 0x0305. The incoming port ID of the unknown Source MAC address and valid bit is reported in register address 0x0306. RW R Default 0
10.9.5. 0x0304H: Unknown SA Capture Register 1
Bits 15:0 Table 60. 0x0304H: Unknown SA Capture Register 1 Name Description UnknownSA[31:16] Unknown Source MAC Address Capture (Byte 2, 3). RW R Default 0
10.9.6. 0x0305H: Unknown SA Capture Register 2
Bits 15:0 Table 61. 0x0305H: Unknown SA Capture Register 2 Name Description UnknownSA[47:32] Unknown Source MAC Address Capture (Byte 4, 5) RW R Default 0
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10.9.7. 0x0306H: Unknown SA Status Register
Bits 4:0 Table 62. 0x0306H: Unknown SA Status Register Name Description UnknownSAPID[4:0] Unknown Source MAC Address Incoming Port ID. When an unknown SA is detected, UnknownSAPID[4:0] reports the Port ID incoming port. UnknownSAstatus Unknown SA Capture Status. When an unknown SA is detected and captured, this bit will be set to `1'. The read sequence is Reg 0x0305 Reg 0x0304 Reg 0x0303. 0: Idle (previous old status) 1: New unknown SA was detected and captured in Unknown SA Management Registers. This bit will be auto cleared after being read. 15:6 Reserved RW R Default 0000
5
RC
0
10.9.8. 0x0307H: Port Trunking Configuration Register
Bits 7:0 Name EnTrunk[7:0] Table 63. 0x0307H: Port Trunking Configuration Register Description Trunk Group Enable/Disable Control Enables trunk groups. EnTrunk[0] control for Trunk 0: (port 0, 1). EnTrunk[1] control for Trunk 1: (port 2, 3). EnTrunk[2] control for Trunk 2: (port 4, 5, 6, 7). EnTrunk[3] control for Trunk 3: (port 8, 9, 10, 11). EnTrunk[4] control for Trunk 4: (port 12, 13, 14, 15). EnTrunk[5] control for Trunk 5: (port 16, 17, 18, 19). EnTrunk[6] control for Trunk 6: (port 20, 21, 22, 23). EnTrunk[7] control for Trunk 7: (port G0, G1). 0: Disable Trunking 1: Enable Trunking Test bit. Keep as 0. The bit value of EEPROM should be set to 0. RW RW Default 0x00
8
PNTest
RW
0
15:8
Reserved
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RTL8326 Datasheet
10.9.9. 0x0308H: IGMP Snooping Control Register
Bits 0 Name EnIGMPsnooping Table 64. 0x0308H: IGMP Snooping Control Register Description Enable IGMP Snooping. The switch controller features an ASIC-based auto IGMP v1 & v2 snooping function. No software support is required. When enabled, the switch can automatically snoop IGMP packets and build up an IP multicast address table. The discovered IP multicast Router port will be indicated in the `IP Multicast Router Port Discovery Register'. 0: Disable IGMP snooping 1: Enable IGMP snooping RW RW Default HW pin. EnIGMP snooping
15:1
Reserved
10.9.10. 0x0309H: IP Multicast Router Port Discovery Register (32 bits)
Table 65. 0x0309H: IP Multicast Router Port Discovery Register (32 bits) Bits Name Description RW 25:0 IPMRouterDISC[25:0] IP Multicast Router Ports Discovery Result. R This is a bit map that indicates which port is an IP Multicast Router port. IPMRouterDISC[25:0] maps to port 25 ~ 0 0: Normal port 1: IP multicast Router port 31:26 Reserved Default 0
10.9.11. 0x030BH: VLAN Control Register
Bits 0 Name EnVlan Table 66. 0x030BH: VLAN Control Register Description Enable VLAN Function. When the VLAN function is enabled, the power on default VLAN topology is 24 Home VLAN for non-EEPROM environments. The VLAN topology can be configured by Port VLAN Configuration Registers. 0: Disable VLAN 1: Enable VLAN Unicast Packet Inter-VLAN Leaky Control Enables inter-VLAN communication for unicast forwarding packets. Normally, inter-VLAN packet switching is not valid. The RTL8326 supports a control bit to enable inter-VLAN communication in the switch without an external router. 0: Disable 1: Enable ARP broadcast Packet Inter-VLAN Leaky Control. Enables inter-VLAN communication for ARP broadcast packet forwarding. 0: Disable 1: Enable 78 RW RW Default HW pin.
EnHomeVLAN
1
EnUCleaky
RW
0
2
EnARPleaky
RW
0
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
Bits 3 Name EnIPMleaky Description IP Multicast Packet Inter-VLAN Leaky Control. Enables inter-VLAN communication for ARP broadcast packet forwarding. 0: Disable 1: Enable Enable 802.1Q VLAN tag aware. If 802.1Q VLAN aware, the switch supports the ability to identify the VLAN ID from the VLAN tag. Reset to force the switch to ignore the VLAN tag header and classify the VLAN only by the PVID. 0: Disable 802.1Q VLAN aware (Default) 1: Enable 802.1Q VLAN aware Ingress Rule for Acceptable frame types control. If this parameter is set to `Admit only VLAN-Tagged Frames', any frames received on that port that carry no VID (i.e., Untagged Frames or Priority-Tagged Frames) are discarded. If this parameter is set to `Admit all Frames', all incoming Priority-Tagged and Untagged Frames are associated with a VLAN by the ingress rule on the receiving port. 0: Admit all Frames (Default) 1: Admit only VLAN-Tagged Frames Ingress Rule for Ingress Filtering control. If the Enable Ingress Filtering parameter `EnIR_MembSet' is set, then all frames received on a port whose VLAN classification does not include that port in its member set shall be discarded. 0: Disable ingress member set Filtering (Default) 1: Enable ingress member set filtering RW RW Default 0
4
En8021Qaware
RW
0
5
EnIR_TagAdmit
RW
0
6
EnIR_MembSet
RW
0
15:7
Reserved
10.9.12. 0x030C~0x0318H: Port VLAN ID Assignment Index Register 0~12
For Port(2n), and Port(2n+1) the register is defined as follows: where n=0, 1, 2, ... 11, 12 (Addr: 0x030CH + n).
Bits 7:0 Table 67. 0x030C~0x0318H: Port VLAN ID Assignment Index Register 0~12 Name Description RW P(2n)_VIDIndex[7:0] Port(2n) VID assignment Index. RW Bit[4:0]: Port VID assignment index. Use the index value as the offset to map to the VLAN configuration table to get a 12-bit Port VLAN ID Bit[7:5]: Reserved, currently not used P(2n+1)_VIDIndex[7:0] Port(2n+1) VID assignment Index. RW Bit[4:0]: Port VID assignment index. Use the index value as the offset to map to the VLAN configuration table to get a 12-bit Port VLAN ID Bit[7:5]: Reserved, current not used Default n
15:8
2n+1
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Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
10.9.13. 0x0319~0x031CH: VLAN Output Port Priority-Tagging Control Register 0, 1, 2, 3
For Port(8n), Port(8n+1), .... ~ Port(8n+7) the register is defined as follows: n=port0~port25.
Table 68. 0x0319~0x031CH: VLAN Output Port Priority-Tagging Control Register 0, 1, 2, 3 Name Description RW Default P(8n)_PriTagCtl[1:0] Port(8n) VLAN Output priority Tag/Untag Control. RW 11 00: Remove the VLAN tag from a tagged frame 01: Insert priority tag into an untagged high-priority frame. (set priority field: 7, VID field: 0 for high priority frame) 10: Insert priority tag into all untagged frames. (set priority field: 7, VID field: 0 for high priority frame; set priority field: 0, VID field: 0 for low priority frame) 11: Don't touch (Don't modify the packet) (Default) P(8n+1)_PriTagCtl[1:0] 3:2 Port(8n+1) VLAN Output priority Tag/Untag Control. RW 11 P(8n+2)_PriTagCtl[1:0] 5:4 Port(8n+2) VLAN Output priority Tag/Untag Control. RW 11 7:6 P(8n+3)_PriTagCtl[1:0] Port(8n+3) VLAN Output priority Tag/Untag Control. RW 11 9:8 P(8n+4)_PriTagCtl[1:0] Port(8n+4) VLAN Output priority Tag/Untag Control. RW 11 11:10 P(8n+5)_PriTagCtl[1:0] Port(8n+5) VLAN Output priority Tag/Untag Control. RW 11 13:12 P(8n+6)_PriTagCtl[1:0] Port(8n+6) VLAN Output priority Tag/Untag Control. RW 11 15:14 P(8n+7)_PriTagCtl[1:0] Port(8n+7) VLAN Output priority Tag/Untag Control. RW 11 Bits 1:0
10.10.
0x031D~0x037CH: VLAN Table Configuration Registers
Each VLAN configuration entry requires three 16-bit registers. There are 32 VLAN configuration entries in the VLAN table. The VLAN configuration entry is combined with three registers: VLAN_Entry_Configuration_0, 1, 2. For VLAN m, its format is defined as follows: m=0, 1, 2, .... 31.
10.10.1. Register VLAN(m)_Entry_Configuration_0 (Addr: (0x031DH+3m))
Bits 15:0 Table 69. Register VLAN(m)_Entry_Configuration_0 (Addr: (0x031DH+3m)) Name Description RW Default VLAN(m)_PM[15:0] VLAN (entry m) Port Member, 26-bit map (bit 0~15). RW Default set to 24+2 Bit value 0: Port is not a member of the VLAN Home VLAN Bit value 1: Port is a member of the VLAN topology
10.10.2. Register VLAN(m)_Entry_Configuration_1 (Addr: (0x031DH+3m+1))
Table 70. Register VLAN(m)_Entry_Configuration_1 (Addr: (0x031DH+3m+1)) Bits Name Description RW Default 9:0 VLAN(m)_PM[25:16] VLAN(m) Port Member 26-bit map (bit 16~25). RW Default set as 24+2 Bit value 0: Port is not a member of the VLAN Home VLAN Bit value 1: Port is a member of the VLAN topology 15:10 Reserved
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Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
10.10.3. Register VLAN(m)_Entry_Configuration_2 (Addr: (0x031DH+3m+2))
Bits 11:0 15:12 Table 71. Register VLAN(m)_Entry_Configuration_2 (Addr: (0x031DH+3m+2)) Name Description RW VLAN(m)_VID[11:0] VLAN(m) VID[11:0] bit 11~0. RW Each VLAN must be assigned a 12-bit VID. Reserved Default 0
10.11.
QoS Configuration Register
Table 72. 0x0400H: QoS Control Register Description Enable TCP/IP TOS/DS (DiffServ) based Priority QoS. 0: Disabled (Default) 1: Enabled When enabled, the priority definition is defined as follows: High Priority: If TOS/DS[0:5]: (EF) `101110'; (AF) `001010', `010010', `011010', `100010'; (Network Control) "11x000' Low Priority: TOS/DS = Other codepoint values Note 1: The DS[0:5] bit location is equal to the mapping of TOS[0:5] ={precedence[2:0], Delay, Throughput, Reliability}. Note 2: DS=Differentiated Services, EF= Expected Forwarding, AF= Assured Forwarding. Enable 802.1p VLAN Tag Based Priority QoS Function. 0: Disable (Default) 1: Enable Enable Flow Control Ability Auto Turn Off for QoS. Enabled: Enables auto turn off of a port's queue flow control ability for 1~2 seconds whenever the port receives a high priority frame. The flow control ability of this port is re-enabled when no high priority frames are received at this port during a 1~2 second period. When EnFCAutoOff is disabled, the flow control ability of this port for any packet will be enabled as it was set. 0: Disabled (Default) 1: Enabled Weighted round robin ratio setting of priority queue. The frame service rate of High-pri queue: Low-pri queue is. 00: 4:1 01: 8:1 10: 16:1 (Default) 11: High priority queue first always
10.11.1. 0x0400H: QoS Control Register
Bits 0 Name EnDSPri RW RW Default HW pin. EnDSPri
1
En8021pPri
RW
HW pin. En8021pPri HW pin. EnFCAutoOff
2
EnFCAutoOff
RW
4:3
QWeight[1:0]
RW
HW pin. QWeight[1:0]
15:5
Reserved 81 Track ID: JATR-1076-21 Rev. 2.1
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
RTL8326 Datasheet
10.11.2. 0x0401: Port Priority Configuration Registers 0
Bits 15:0 Name PortPriCfg[15:0] Table 73. 0x0401: Port Priority Configuration Registers 0 Description Port based Priority setting (Port0 ~ Port15). Sets the priority QoS based on the physical port. If a port is set as a high priority port, all packets received from that port will be treated as high priority packets. Bit value 1: Sets that port as a high priority port Bit value 0: Sets that port as a low priority port Note: Ports 0~15 map to bits 0~ 15. RW RW Default
Bit[15:4]=0; Bit[3:0].depend on HW pin. PortPriSet[1:0]
10.11.3. 0x0402: Port Priority Configuration Registers 1
Bits 9:0 Table 74. 0x0402: Port Priority Configuration Registers 1 Name Description PortPriCfg[25:16] Port based Priority setting (Port16 ~ Port25). Sets the priority QoS based on the physical port. If a port is set as a high priority port, all packets received from that port will be treated as high priority packets. Bit value 1: Sets that port as a high priority port Bit value 0: Sets that port as a low priority port Note: Ports 16~25 map to bits 0~ 9. Reserved RW RW Default 0
15:10
10.12.
PHY Access Control Register
Table 75. 0x0500H: PHY Access Control Register Description PHY Register address setting for the PHY Access command. PHY ID (PHY address) setting for the PHY Access command. RTL8326 connected PHY ID is fixed as: Fast Ethernet Port0 ~ 23. PHY ID: 8, 9, ..., 30, 31. Gigabit Port G1 and G2. PHY ID: 2 and 3. PHY Access Command. 0: PHY Access Read command 1: PHY Access Write command PHY Access Command Execution Status. 0: Idle 1: Busy
10.12.1. 0x0500H: PHY Access Control Register
Bits 4:0 9:5 Name REG_addr PHY_ID[4:0] RW RW RW Default 0 0
13:10 14
Reserved PHY_RW
RW
0 0
15
PHYCmdExeSta
R
0
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RTL8326 Datasheet
10.12.2. 0x0501H: PHY Access Write Data Register
Bits 15:0 Name PHY_WD[15:0] Table 76. 0x0501H: PHY Access Write Data Register Description PHY Access Write Out Data (16 bits). RW RW Default 0
10.12.3. 0x0502H: PHY Access Read Data Register
Bits 15:0 Name PHY_RD[15:0] Table 77. 0x0502H: PHY Access Read Data Register Description PHY Access Read In Data (16 bits). RW R Default 0
10.13.
Port Control Register
Table 78. 0x0607H: Global Port Control Register Description Disable Full Duplex Flow Control (802.3x PAUSE ability). This control bit will be applied to the switch only when a software reset is sent to the switch. This function can also be directly controlled by PHY register access through the PHY Access Control Register 0: Enable 802.3x Pause ability 1: Disable 802.3x Pause ability Globally Disable Half Duplex Back Pressure Flow Control Ability. Set to globally disable the back pressure flow control ability of all ports. 0: Enable back pressure flow control ability 1: Disable back pressure flow control ability Disable Broadcast Packet Strict Flood Control. Set to disable broadcast packet (DA: `FFFFFFFFFFFF') strict flood mode and configure to loose flood mode. The control function is used under 802.3x flow control mode. Strict flood mode will drop broadcast packets if any one destination port member is congested. Loose flood mode allows broadcast packets to be flooded to all non-congested ports. 0: Disable Broadcast Packet Strict Flood (Loose flood mode) 1: Enable Broadcast Packet Strict Flood (Strict flood mode) Disable IP Multicast Packet Strict Flood Control. Set to disable IP Multicast packet (DA: `01-00-5E-XX-XXXX') strict flood mode and configure to loose flood mode. The control function is used under 802.3x flow control mode. Strict flood mode will drop IP Multicast packets if any one destination port member is congested. Loose flood mode allows IP multicast packets to be flooded to all non-congested ports. 0: Disable IP Multicast Packet Strict Flood (Loose flood mode) 1: Enable IP Multicast Packet Strict Flood (Strict flood mode) 83
10.13.1. 0x0607H: Global Port Control Register
Bits 0 Name DisFDFC RW RW Default HW pin: DisFDFC
1
DisBKP
RW
HW pin. DisBKP
2
DisBCSFC
RW
HW pin. DisBCFC
3
DisIPMSFC
RW
HW pin. DisIPMFC
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
Bits 4 Name DisBRDCTRL Description Disable Broadcast Storm Filtering Control. Set to disable the broadcast storm filtering control function. 1: Disable Broadcast storm filtering control (Default) 0: Enable Broadcast storm filtering control RW RW Default HW pin: DisBRDCTRL
15:5
Reserved
10.13.2. 0x0608H: Port Disable Control Register 0
Bits 15:0 Name PortDisable[15:0] Table 79. 0x0608H: Port Disable Control Register 0 Description Port Enable/Disable Control for port 0 ~ 15. Bit value 0: Port enable Bit value 1: Port disable When disabled, the port will disable packet transmission and reception except for Realtek Remote Control Packets. Note: Ports 0~15 map to bits 0~ 15. RW RW Default 0
10.13.3. 0x0609H: Port Disable Control Register 1
Bits 9:0 Name PortDisable[25:16] Table 80. 0x0609H: Port Disable Control Register 1 Description Port Enable/Disable Control for port 16 ~ 25. Bit value 0: Port enable Bit value 1: Port disable When disabled, the port will disable packet transmission and reception except for Realtek Remote Control Packets. Note: Ports 16~25 map to bits 0~ 9. RW RW Default 0
15:10
Reserved
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
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Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
10.13.4. 0x060AH~0x0616. Port Property Configuration Register 0 ~ 12
For Port(2n) and Port(2n+1) the Port Property is defined as follows: n = 0, 1, 2,. ..., 12 (Addr: 0x060AH +n); where n=0~11 for Fast Ethernet ports, n=12 for Gigabit ports).
Bits 7:0 Table 81. 0x060AH~0x0616. Port Property Configuration Register 0 ~ 12 Name Description RW P(2n)_Property[7:0] Port(2n) Port Property configuration. RW Bit [4:0]: Media Capability[4:0]= (1000F, 100F, 100H, 10F, 10H). Bit [5]: Pause ability (1: Enable). Bit [6]: AsyPause ability (Asynchronous Pause) (1. enable) Bit [7]: Enable Auto Negotiation (1: Enable). Note: A software reset is required to complete the port properties update. P(2n+1)_Property[7:0] Port(2n+1) Port property configuration. RW Bit [4:0]: Media Capability[4:0]= {1000F, 100F, 100H, 10F, 10H}. Bit [5]: Pause ability (1: Enable). Bit [6]: AsyPause ability ( Asynchronous Pause) (1: Enable). Bit [7]: Enable Auto Negotiation (1: Enable). Note: A software reset is required to complete the port properties update. Default 100M. 0xAF 1000M: 0xBF
15:8
100M. 0xAF 1000M: 0xBF
Note: A configuration update of these registers requires a software reset (via write Reg. 0x0000 bit 0 =1) to force the configuration to be written to the PHY register and restart the auto-negotiation process.
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RTL8326 Datasheet
10.13.5. 0x0619H~0x0625. Port Link Status Register 0 ~ 12
For Port(2n) and Port(2n+1) the Port Properties are defined as follows: (n: 0,1,2,. ..., 12) (Addr: 0x060AH +n).
Bits 7:0 Table 82. 0x0619H~0x0625. Port Link Status Register 0 ~ 12 Name Description P(2n)_LinkStatus[7:0] Port (2n) Port Link Status. Bit [1:0]: Link speed[1:0]: 00: 10Mbps 01: 100Mbps 10: 1000Mbps 11: NA. Bit [2]: Full duplex: 0: Half duplex 1: Full duplex Bit[3]: Reserved. Bit [4]: Link up: 0: Link down 1: Link up Bit [5]: Flow control (back pressure or 802.3x): For ports 0~23 (Fast Ethernet ports). Defined as Pause ability. For ports 24~25 (Gigabit ports). Defined as TX Pause ability. In half duplex mode. Defined as back pressure ability. 0: Flow control disabled 1: Flow control enabled Bit [6]: AsyPause ability (Asymmetric Pause): For ports 0~23 (Fast Ethernet ports) Don't Care. For ports 24~25 (Gigabit ports). Defined as RX Pause ability. In half duplex mode. Don't Care. 0: Flow control disabled 1: Flow control enabled Bit [7]: Enable Auto Negotiation (AN): 0: Disable AN 1: Enable AN RW R Default 0
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RTL8326 Datasheet
Bits 15:8 Name Description
P(2n+1)_LinkStatus[7:0] Port(2n+1) Port Link Status.
RW R
Default 0
Bit [1:0]: Link speed[1:0]: 00: 10Mbps 01: 100Mbps 10: 1000Mbps 11: NA. Bit [2]: Full duplex: 0: Half duplex 1: Full duplex Bit[3]: Reserved. Bit [4]: Link up: 0: Link down 1: Link up Bit [5]: Flow Control (back pressure or 802.3x): For ports 0~23 (Fast Ethernet ports). Defined as Pause ability. For ports 24~25 (Gigabit ports). Defined as TX Pause ability. In half duplex mode. Defined as back pressure ability. 0: Flow control disabled 1: Flow control enabled Bit [6]: AsyPause ability (Asymmetric Pause): For ports 0~23 (Fast Ethernet ports) Don't Care. For ports 24~25 (Gigabit ports). Defined as RX Pause ability. In half duplex mode. Don't Care. 0: Flow control disabled 1: Flow control enabled Bit [7]: Enable Auto Negotiation (AN): 0: Disable AN 1: Enable AN
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RTL8326 Datasheet
11.
MIB Counter Register
11.1. 0x0700H ~ 0x070CH: Port MIB Counter Object Selection Register 0 ~ 12
For Port(2n), Port(2n+1), the Port MIB Counter Object Selection Register is defined as follows: n = 0, 1, 2, ..., 12) (Addr=0x0700H +n)
Bits 1:0 Table 83. 0x0700H ~ 0x070CH: Port MIB Counter Object Selection Register 0 ~ 12 Name Description RW Default RW 01 P(2n)CNT1_MIBS [1:0] Port(2n) Counter_1 MIB Object Selection P(2n)CNT_1_MIBS [1:0] 00: MIB object: RX byte count 01: MIB object: RX packet count (Default) 10: MIB object: CRC error packet count 11: MIB object: Collision packet count RX byte count. This counter is incremented once for every data byte of a received and forwarded packet (includes both good and bad packets). RX packet count. This counter is incremented once for every received and forwarded packet (includes both good and bad packets). Port(2n) Counter_2 MIB Object Selection P(2n)CNT_2_MIBS [1:0] 00: MIB object: TX byte count 01: MIB object: TX packet count (Default) 10: MIB object: CRC error packet count 11: MIB object: Collision packet count TX byte count. This counter is incremented once for every data byte of a transmitted packet (includes both good and bad packets). TX packet count. This counter is incremented once for every transmitted packet (includes both good and bad packets).
3:2
P(2n)CNT2_MIBS [1:0]
RW
01
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
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Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
Bits 5:4 Name P(2n)CNT3_MIBS [1:0] Description Port(2n) Counter_3 MIB Object Selection P(2n)CNT_3_MIBS [1:0] 00: MIB object: Drop byte count 01: MIB object: Drop packet count (Default) 10: MIB object: CRC error packet count 11: MIB object: Collision packet count RW RW Default 01
Drop packet count. This counter is incremented once for every drop of a received packet. Packet drop events could be due to undersize, oversize, CRC error, lack of resources, local packet, point-to-point control packet (ex. Pause packet, LACP packet, including RRCP(R) packets). CRC error packet count. This counter is incremented once for every received packet with a valid length but with a CRC error. Collision packet counter. This counter is incremented once for every collision event detected. 7:6 P(2n+1)CNT1_MIBS [1:0] Port(2n+1) Counter_1 MIB Object Selection. 9:8 P(2n+1)CNT2_MIBS [1:0] Port(2n+1) Counter_2 MIB Object Selection. 11:10 P(2n+1)CNT3_MIBS [1:0] Port(2n+1) Counter_3 MIB Object Selection.
RW RW RW
01 01 01
11.2. 0x070DH ~0726H: Port MIB Counter 1 Register (RX Counter) (32 bits)
The MIB counters are 32-bit counters. After power on reset, the counters are all reset to 0. A read access of the MIB counter will NOT reset the counter to 0. When a MIB counter MIB object is changed, then the counter will be reset to 0 and the count will restart. The time before the next read of the same counter should not be longer than the counter's timeout. The timeout of the 32-bit MIB counter depends on the object type and the port speed, and is calculated as follows: Packet counter timeout is calculated based on 64-byte packets and byte counter timeout is calculated based on 1518 byte packets).
Port Speed 1000Mbps 100Mbps 10Mbps Table 84. MIB Counter Timeout MIB Object Type MIB Counter Timeout (Sec.) Packet count 2886 Byte count 34 Packet count 28862 Byte count 348 Packet count 288621 Byte count 3481
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
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Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
11.2.1. For Port(n) MIB Counter 1 Register (32-bit). n=0, 1, 2, ... 25 (Addr: 0x070DH+n)
Bits 31:0 Table 85. 0x070DH ~0726H: Port MIB Counter 1 Register (RX Counter) (32 bits) Name Description RW Port(n)_MIB_CNT_1[31:0] Port(n) MIB Counter_1[31:0] R Default 0
11.2.2. 0x0727~0740H: Port MIB Counter 2 Register (TX Counter) (32-bits)
For Port(n) MIB Counter 2 Register (32-bit): n = 0, 1, 2, ... 25 (Addr: 0x0727H+n).
Bits 31:0 Table 86. 0x0727~0740H: Port MIB Counter 2 Register (TX Counter) (32 bits) Name Description RW Port(n)_MIB_CNT_2[31:0] Port(n) MIB Counter_2[31:0] R Default 0
11.2.3. 0x0741~075AH: Port MIB Counter 3 Register (Diagnostic Counter) (32-bits)
For Port(n) MIB Counter 3 Register (32-bit): n = 0, 1, 2, ... 25 (Addr: 0x0741H+n).
Bits 31:0 Table 87. 0x0741~075AH: Port MIB Counter 3 Register (Diagnostic Counter) (32 bits) Name Description RW Default Port(n)_MIB_CNT_3[31:0] Port(n) MIB Counter_3[31:0] R 0
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RTL8326 Datasheet
12.
Characteristics
12.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise specified.
Parameter Storage Temperature Vcc Supply Referenced to GND Digital Input Voltage DC Output Voltage Table 88. Electrical Characteristics/Ratings Min Max -55 +150 -0.5 +5.0 -0.5 VDD -0.5 VDD Units C V V V
12.2. Operating Range
Parameter Ambient Operating Temperature (Ta) 3.3V VDD Supply Voltage Range Min 0 3 Max +70 3.6 Units C V
12.3. DC Characteristics
Supply Voltage VDD: 3.3V 5%.
Parameter Power Supply Current Symbol Icc Table 89. DC Characteristics Conditions 24FE+2G, wire-speed traffic load 24FE, wire-speed traffic load 16FE+2G, wire-speed traffic load 2G, wire-speed traffic load 24FE+2G all idle 24FE+2G, wire-speed traffic load 24FE, wire-speed traffic load 16FE+2G, wire-speed traffic load 2G, wire-speed traffic load 24FE+2G all idle Min Typical Max 480 340 430 330 190 1584 1122 1419 1089 627 0.8 10 2.9 2.6 0 3.6 0.4 Units mA
Total Power Consumption
PS
mW
TTL Input High Voltage TTL Input Low Voltage TTL Input Current TTL Input Capacitance Output High Voltage Output Low voltage
Vih Vil Iin Cin Voh Vol
2.0 -10
V V uA pF V V
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RTL8326 Datasheet
12.4. Digital Timing Characteristics
12.4.1. PHY Management (SMI) Timing
Symbol Table 90. PHY Management (SMI) Timing Description Minimum Typical MDC clock period 1360 MDC high level width 680 MDC low level width 680 MDIO to MDC rising setup time (Write 680 Bits) MDIO to MDC rising hold time (Write Bits) 680 MDC to MDIO delay (Read Bits) MDC/MDIO actives from RST# deasserted 45 Maximum 20 Units ns ns ns ns ns ns ms
t1 t2 t3 t4 t5 t6 t7
t1 t2 t3
MDC
t4 t5
MDIO
Data
Figure 18. MDC/MDIO Write Timing
t1 t2 t3
MDC
t6
MDIO
Data
Figure 19. MDC/MDIO Read Timing
RST# MDC MDIO
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
t7
High High
Figure 20. MDC/MDIO Reset Timing 92 Track ID: JATR-1076-21 Rev. 2.1
RTL8326 Datasheet
12.4.2. SMII Transmit Timing
Symbol
T_opd_txd_smii
Table 91. PHY Management (SMI) Timing Description Minimum Typical REFCLK rising edge to TXD (SYNC) 2 4 delay.
Maximum 5
Units ns
T_opd_txd_smii
REFCLK TXD SYNC
Figure 21. SMII Transmit Timing
12.4.3. SMII Receive Timing
Symbol
a T_ipsu_rxd_smii a T_iphd_rxd_smii
a.
Table 92. SMII Receive Timing Description Minimum RXD setup time to REFCLK. 2 RXD hold time from REFCLK. 1.5
Typical
Maximum
Units ns ns
When SMII RXD delay option set to 2ns (refer to 10.1.3 0x0002H: RX I/O PAD Delay Configuration, page 66).
T_ipsu_rxd_smii T_iphd_rxd_smii
REFCLK
RXD
Valid Data
Figure 22. SMII Receive Timing
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RTL8326 Datasheet
12.4.4. GMII Transmit Timing
Symbol T_opd_txd_gmii Table 93. GMII Transmit Timing Description Minimum GxTX_CLK rising edge to TXD delay. 1.2
T_opd_txd_gmii
GxTX_CLK
Typical 2.5
Maximum 4
Units ns
TXD
Figure 23. GMII Transmit Timing
12.4.5. GMII Receive Timing
Symbol T_su_rxd_gmii T_hd_rxd_gmii Table 94. GMII Receive Timing Description Minimum RXD(RX_DV) setup time to 2.5 GxRX_CLK. RXD(RX_DV) hold time from 0.5 GxRX_CLK.
T_su_rxd_gmii T_hd_rxd_gmii
Typical
Maximum
Units ns ns
GxRX_CLK
RXD
Valid Data
Figure 24. GMII Receive Timing
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
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RTL8326 Datasheet
12.4.6. MII Transmit Timing
Symbol T_opd_txd_mii Table 95. MII Transmit Timing Description Minimum GxTXC rising edge to TXD delay. 4
T_opd_txd_mii
Typical 7.4
Maximum 10
Units ns
GxTXC
TXD
Figure 25. MII Transmit Timing
12.4.7. MII Receive Timing
Symbol T_su_rxd_mii T_hd_rxd_mii Table 96. MII Receive Timing Description Minimum RXD(RX_DV) setup time to GxRXC. 2 RXD(RX_DV) hold time from GxRXC. 1
T_su_rxd_mii T_hd_rxd_mii
Typical
Maximum
Units ns ns
GxRXC
RXD
Valid Data
Figure 26. MII Receive Timing
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller
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RTL8326 Datasheet
12.4.8. TBI Transmit Timing
Symbol T_opd_txd_TBI Table 97. TBI Transmit Timing Description Minimum GxTX_CLK rising edge to TXD delay. 1.5
T_opd_txd_TBI
Typical 2.5
Maximum 4
Units ns
GxTX_CLK
TXD
Figure 27. TBI Transmit Timing
12.4.9. TBI Receive Timing
Symbol T_su_rxd_TBI T_hd_rxd_TBI Table 98. TBI Receive Timing Description Minimum RXD setup time to GxRSCK0/1. 3 RXD hold time from GxRSCK0/1. 0.5
T_su_rxd_TBI T_hd_rxd_TBI
Typical
Maximum
Units ns ns
GxRCK0/1
RXD
Valid Data
Figure 28. TBI Receive Timing
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RTL8326 Datasheet
12.5. Thermal Data
Heat generated by the chip causes a temperature rise of the package. If the temperature of the chip (Tj, junction temperature) is beyond the design limits, there will be negative effects on operation and the life of the IC package. Heat dissipation, either through a heat sink or electrical fan, is necessary to provide a reasonable environment (Ta, ambient temperature) in a closed case. As power density increases, thermal management becomes more critical. A method to estimate the possible Ta is outlined below. Thermal parameters are defined as below according to JEDEC standard JESD 51-2, 51-6: 1. ja (Thermal resistance from junction to ambient), represents resistance to heat flow from the chip to ambient air. This is an index of heat dissipation capability. A lower ja means better thermal performance. ja = (Tj - Ta) / Ph Where Tj is the junction temperature Ta is the ambient temperature Ph is the power dissipation 2. jc (Thermal resistance from junction to case), represents resistance to heat flow from the chip to the package top case. jc is important when an external heat sink is attached on the package top. jc = (Tj - Tc) / Ph, where Tj is the junction temperature and Tc is the case temperature.
Ta Tj Tc
Figure 29. Cross-section of 208 PQFP Table 99. Thermal Operating Range Condition
Parameter Junction operating temperature Ambient operating temperature
SYM Tj Ta
Min 0 0
Typical Max 25 125 25 70
Units C C
Parameter Thermal resistance: junction to ambient Thermal resistance: junction to case
SYM ja jc
Table 100. Thermal Resistance Condition 2 layer PCB, 0 ft/s airflow. 2 layer PCB, 0 ft/s airflow.
Min
Typical Max 33.7 1.4
Units C/W C/W
* PCB conditions (JEDEC JESD51-7). Dimensions: 300 x 140 mm. Thickness: 1.6mm
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RTL8326 Datasheet
13.
Mechanical Information
See the Mechanical Dimensions notes on the next page.
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RTL8326 Datasheet
13.1. Mechanical Dimensions Notes
Symbol Dimension in inch Min Typ Max A 0.136 0.144 0.152 A1 0.004 0.010 0.036 A2 0.119 0.128 0.136 b 0.004 0.008 0.012 c 0.002 0.006 0.010 D 1.093 1.102 1.112 E 1.093 1.102 1.112 e 0.012 0.020 0.031 HD 1.169 1.205 1.240 HE 1.169 1.205 1.240 L 0.010 0.020 0.030 L1 0.041 0.051 0.061 y 0.004 0 12 Dimension in mm Min Typ Max 3.45 3.65 3.85 0.10 0.25 0.91 3.02 3.24 3.46 0.10 0.20 0.30 0.04 0.15 0.26 27.75 28.00 28.25 27.75 28.00 28.25 0.30 0.50 0.80 29.70 30.60 31.50 29.70 30.60 31.50 0.25 0.50 0.75 1.05 1.30 1.55 0.10 0 12 Notes: 1.Dimensions D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion. 3.Controlling dimension: Millimeter 4.General appearance spec. should be based on final visual inspection spec. TITLE. 208 PQFP ( 28x28 mm) FOOTPRINT 2.6mm PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: APPROVE DOC. NO. 530-ASS-P004 VERSION 1 PAGE CHECK DWG NO. Q208 - 1 DATE REALTEK SEMICONDUCTOR CORP.
Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller 99 Track ID: JATR-1076-21 Rev. 2.1

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